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參數資料
| 型號： | AD9831 |
| 廠商： | Analog Devices, Inc. |
| 元件分類： | XO, clock |
| 英文描述： | CMOS Complete DDS |
| 中文描述： | 完整的DDS的CMOS |
| 文件頁數： | 11/16頁 |
| 文件大小： | 172K |
| 代理商： | AD9831 |
AD9831
–11–
REV. A
MCLK cycle introduced otherwise. When these inputs change
value, there will be a pipeline delay before control is transferred
to the selected register—there will be a pipeline delay before the
analog output is controlled by the selected register. T here is a
similar delay when a new word is written to a register. PSEL0,
PSEL1, FSELECT and
WR
have latencies of six MCLK cycles.
T he flow chart in Figure 22 shows the operating routine for the
AD9831. When the AD9831 is powered up, the part should be
reset using
RESET
. T his will reset the phase accumulator to
zero so that the analog output is at midscale.
RESET
does not
reset the phase and frequency registers. T hese registers will
contain invalid data and, therefore, should be set to zero by the
user.
T he registers to be used should be loaded, the analog output
being f
MCLK
/2
32
×
FREG where FREG is the value loaded into
the selected frequency register. T his signal will be phase shifted
by the amount specified in the selected phase register (2
π
/4096
×
PHASEREG where PHASEREG is the value contained in the
selected phase register). When FSELECT , PSEL0 and PSEL1
are programmed, there will be a pipeline delay of approximately
6 MCLK cycles before the analog output reacts to the change
on these inputs.
DATA WRITE
FREG<0, 1> = 0
PHASEREG<0, 1, 2, 3> = 0
DATA WRITE
FREG<0> = f
OUT0
/f
MCLK
*2
32
FREG<1> = f
OUT1
/f
MCLK
*2
32
PHASEREG<3:0> = DELTA PHASE<0, 1, 2, 3>
SELECT DATA SOURCES
SET FSELECT
SET PSEL0, PSEL1
DAC OUTPUT
V
OUT
= V
REFIN
*6.25*R
OUT
/R
SET*
(1 + SIN(2
π
(FREG*f
MCLK
*t/2
32
+ PHASEREG/2
12
)))
WAIT 6 MCLK CYCLES
CHANGE PHASE
CHANGE F
OUT
CHANGE FREG
YES
CHANGE PHASEREG
CHANGE PSEL0, PSEL1
YES
NO
NO
YES
NO
YES
NO
RESET
CHANGE FSELECT
Figure 22. Flow Chart for AD9831 Initialization and Operation
DSP and MPU Interfacing
T he AD9831 has a parallel interface, with 16 bits of data being
loaded during each write cycle.
T he frequency or phase registers are loaded by asserting the
WR
signal. T he destination register for the 16 bit data is selected
using the address inputs A0, A1 and A2. T he phase registers
are 12 bits wide so, only the 12 LSBs need to be valid—the
4 MSBs of the 16 bit word do not have to contain valid data.
Data is loaded into the AD9831 by pulsing
WR
low, the data
being latched into the AD9831 on the rising edge of
WR
. T he
values of inputs A0, A1 and A2 are also latched into the
AD9831 on the
WR
rising edge. T he appropriate destination
register is updated on the next MCLK rising edge. If the
WR
rising edge coincides with the MCLK rising edge, there is an
uncertainty of one MCLK cycle regarding the loading of the
destination register—the destination register may be loaded
immediately or the destination register may be updated on the
next MCLK rising edge. T o avoid any uncertainty, the times
listed in the specifications should be complied with.
FSELECT , PSEL0 and PSEL1 are sampled on the MCLK
rising edge. Again, these inputs should be valid when an
MCLK rising edge occurs as there will be an uncertainty of one
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相關代理商/技術參數 |
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|---|---|
| AD9831AST | 制造商:Rochester Electronics LLC 功能描述:25 MHZ +5V/+3V, 10-BIT DDS DAC I.C. - Bulk 制造商:Analog Devices 功能描述:10BIT DAC DDS 25 MHZ +5V/+3V 9831 |
| AD9831AST-REEL | 制造商:Analog Devices 功能描述:Direct Digital Synthesizer 25MHz 1-DAC 10-Bit Parallel 48-Pin LQFP T/R 制造商:Rochester Electronics LLC 功能描述:25 MHZ +5V/+3V, 10-BIT DDS DAC I.C. - Tape and Reel |
| AD9831ASTZ | 功能描述:IC DDS 10BIT 25MHZ CMOS 48-LQFP RoHS:是 類別:集成電路 (IC) >> 接口 - 直接數字合成 (DDS) 系列:- 產品變化通告:Product Discontinuance 27/Oct/2011 標準包裝:2,500 系列:- 分辨率（位）:10 b 主 fclk:25MHz 調節字寬（位）:32 b 電源電壓:2.97 V ~ 5.5 V 工作溫度:-40°C ~ 85°C 安裝類型:表面貼裝 封裝/外殼:16-TSSOP（0.173"，4.40mm 寬） 供應商設備封裝:16-TSSOP 包裝:帶卷 (TR) |
| AD9831ASTZKL1 | 制造商:Rochester Electronics LLC 功能描述: 制造商:Analog Devices 功能描述: |
| AD9831ASTZ-REEL | 功能描述:IC DDS 10BIT 25MHZ CMOS 48TQFP RoHS:是 類別:集成電路 (IC) >> 接口 - 直接數字合成 (DDS) 系列:- 產品變化通告:Product Discontinuance 27/Oct/2011 標準包裝:2,500 系列:- 分辨率（位）:10 b 主 fclk:25MHz 調節字寬（位）:32 b 電源電壓:2.97 V ~ 5.5 V 工作溫度:-40°C ~ 85°C 安裝類型:表面貼裝 封裝/外殼:16-TSSOP（0.173"，4.40mm 寬） 供應商設備封裝:16-TSSOP 包裝:帶卷 (TR) |
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