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參數資料
型號: AD9832
廠商: Analog Devices, Inc.
元件分類: XO, clock
英文描述: CMOS Complete DDS
中文描述: 完整的CMOS的直接數字合成器
封裝: TSSOP-16
文件頁數: 2/16頁
文件大小: 146K
代理商: AD9832
–2–
REV. A
AD9832–SPECIFICATIONS
1
(V
DD
= +3.3 V
6
10%; +5 V
6
10%; AGND = DGND = 0 V; T
A
= T
MIN
to T
MAX
; REFIN =
REFOUT; R
SET
= 3.9 k
V
; R
LOAD
= 300
V
for IOUT unless otherwise noted)
Parameter
AD9832B
Units
Test Conditions/Comments
SIGNAL DAC SPECIFICATIONS
Resolution
Update Rate (f
MAX
)
I
OUT
Full Scale
10
25
4
4.5
1.35
Bits
MSPS nom
mA
nom
mA max
V max
Output Compliance
DC Accuracy
Integral Nonlinearity
Differential Nonlinearity
DDS SPECIFICATIONS
2
Dynamic Specifications
Signal to Noise Ratio
Total Harmonic Distortion
Spurious Free Dynamic Range (SFDR)
3
Narrow Band (
±
50 kHz)
3 V Power Supply
±
1
±
0.5
LSB typ
LSB typ
50
–53
dB min
dBc max
f
MCLK
= 25 MHz, f
OUT
= 1 MHz
f
MCLK
= 25 MHz, f
OUT
= 1 MHz
f
MCLK
= 6.25 MHz, f
OUT
= 2.11 MHz
5 V Power Supply
3 V Power Supply
–72
–70
–50
–60
1
Yes
dBc min
dBc min
dBc min
dBc typ
ms typ
Wide Band (
±
2 MHz)
Clock Feedthrough
Wake-Up Time
4
Power-Down Option
VOLTAGE REFERENCE
Internal Reference @ +25
°
C
T
MIN
to T
MAX
REFIN Input Impedance
Reference TC
REFOUT Output Impedance
LOGIC INPUTS
V
INH
, Input High Voltage
V
INL
, Input Low Voltage
I
INH
, Input Current
C
IN
, Input Capacitance
POWER SUPPLIES
AVDD
DVDD
I
AA
I
DD
I
AA
+ I
DD5
1.21
1.21
±
7%
10
100
300
Volts typ
Volts min/max
M
typ
ppm/
°
C typ
typ
V
DD
– 0.9
0.9
10
10
V
min
V
max
μ
A
max
pF
max
2.97/5.5
2.97/5.5
5
2.5 + 0.4/MHz
15
24
350
V
min/V
max
V
min/V
max
mA
max
mA typ
mA
max
mA
max
μ
A max
5 V Power Supply
5 V Power Supply
3 V Power Supply
5 V Power Supply
Low Power Sleep Mode
NOTES
1
Operating temperature range is as follows: B Version, –40
°
C to +85
°
C.
2
100% production tested.
3
f
= 6.25 MHz, Frequency Word = 5671C71C HEX, f
= 2.11 MHz.
4
See Figure 11. To reduce the wake-up time at low power supplies and low temperature, the use of an external reference is suggested.
5
Measured with the digital inputs static and equal to 0 V or DVDD.
The AD9832 is tested with a capacitive load of 50 pF. The part can be operated with higher capacitive loads, but the magnitude of the analog output will be attenuated.
For example, a 5 MHz output signal will be attenuated by 3 dB when the load capacitance equals 85 pF.
Specifications subject to change without notice.
IOUT
COMP
REFIN
FS
ADJUST
REFOUT
12
AD9832
ON-BOARD
REFERENCE
10-BIT DAC
SIN
ROM
FULL-SCALE
CONTROL
300
50pF
R
SET
3.9k
10nF
10nF
AVDD
Figure 1. Test Circuit with Which Specifications Are Tested
相關PDF資料
PDF描述
AD9832BRU CMOS Complete DDS
AD9833 +2.5 V to +5.5 V, 25 MHz Low Power CMOS Complete DDS
AD9833BRM +2.5 V to +5.5 V, 25 MHz Low Power CMOS Complete DDS
AD9834 Low Power, +2.3 V to +5.5 V, 50 MHz Complete DDS
AD9834BRU Low Power, +2.3 V to +5.5 V, 50 MHz Complete DDS
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