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參數(shù)資料
| 型號： | AD9854/PCBZ |
| 廠商： | Analog Devices Inc |
| 文件頁數(shù)： | 1/52頁 |
| 文件大小： | 0K |
| 描述： | BOARD EVAL FOR AD9854 |
| 產品培訓模塊： | Direct Digital Synthesis Tutorial Series (1 of 7): Introduction Direct Digital Synthesizer Tutorial Series (7 of 7): DDS in Action Direct Digital Synthesis Tutorial Series (3 of 7): Angle to Amplitude Converter Direct Digital Synthesis Tutorial Series (6 of 7): SINC Envelope Correction Direct Digital Synthesis Tutorial Series (4 of 7): Digital-to-Analog Converter Direct Digital Synthesis Tutorial Series (2 of 7): The Accumulator |
| 設計資源： | AD9854 Eval Brd Schematic AD9854 Eval Brd BOM |
| 標準包裝： | 1 |
| 系列： | AgileRF™ |
| 主要目的： | 計時，直接數(shù)字合成（DDS） |
| 已用 IC / 零件： | AD9854 |
| 已供物品： | 板 |
| 相關產品： | AD9854ASTZ-ND - IC DDS QUADRATURE CMOS 80-LQFP |
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CMOS 300 MSPS Quadrature
Complete DDS
AD9854
Rev. E
Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibilityis assumedbyAnalogDevicesforitsuse,norforanyinfringements of patents or other
rightsofthirdpartiesthatmayresultfromitsuse.Specificationssubjecttochangewithoutnotice.No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarksandregisteredtrademarksarethepropertyoftheirrespectiveowners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700
www.analog.com
Fax: 781.461.3113
2002–2007 Analog Devices, Inc. All rights reserved.
FEATURES
300 MHz internal clock rate
FSK, BPSK, PSK, chirp, AM operation
Dual integrated 12-bit digital-to-analog converters (DACs)
Ultrahigh speed comparator, 3 ps rms jitter
Excellent dynamic performance
80 dB SFDR at 100 MHz (±1 MHz) AOUT
4× to 20× programmable reference clock multiplier
Dual 48-bit programmable frequency registers
Dual 14-bit programmable phase offset registers
12-bit programmable amplitude modulation and
on/off output shaped keying function
Single-pin FSK and BPSK data interfaces
PSK capability via input/output interface
Linear or nonlinear FM chirp functions with single-pin
frequency hold function
Frequency-ramped FSK
<25 ps rms total jitter in clock generator mode
Automatic bidirectional frequency sweeping
Sin(x)/x correction
Simplified control interfaces
10 MHz serial 2- or 3-wire SPI compatible
100 MHz parallel 8-bit programming
3.3 V single supply
Multiple power-down functions
Single-ended or differential input reference clock
Small, 80-lead LQFP or TQFP with exposed pad
APPLICATIONS
Agile, quadrature LO frequency synthesis
Programmable clock generators
FM chirp source for radar and scanning systems
Test and measurement equipment
Commercial and amateur RF exciters
FUNCTIONAL BLOCK DIAGRAM
DIGITAL MULTIPLIERS
SYSTEM
CLOCK
DAC RSET
INV
SINC
FILTER
FR
E
Q
U
E
N
C
Y
A
C
UMUL
A
T
O
R
AC
C
1
I/O PORT BUFFERS
COMPARATOR
PROGRAMMING REGISTERS
DIFF/SINGLE
SELECT
REFERENCE
CLOCK IN
FSK/BPSK/HOLD
DATA IN
BIDIRECTIONAL
INTERNAL/EXTERNAL
I/O UPDATE CLOCK
READ
WRITE
SERIAL/
PARALLEL
SELECT
6-BIT ADDRESS
OR SERIAL
PROGRAMMING
LINES
8-BIT
PARALLEL
LOAD
MASTER
RESET
+VS
GND
CLOCK
OUT
ANALOG
IN
OSK
ANALOG
OUT
ANALOG
OUT
P
HAS
E
-T
O
-
A
M
P
LITU
D
E
CO
NV
E
RT
E
R
PROGRAMMABLE
AMPLITUDE AND
RATE CONTROL
D
Q
CK
÷2
INT
EXT
SYSTEM
CLOCK
REF
CLK
BUFFER
SYSTEM
CLOCK
MUX
DELTA
FREQUENCY
RATE TIMER
SYSTEM
CLOCK
DELTA
FREQUENCY
WORD
FREQUENCY
TUNING
WORD 1
FREQUENCY
TUNING
WORD 2
FIRST 14-BIT
PHASE/OFFSET
WORD
SECOND 14-BIT
PHASE/OFFSET
WORD
12-BIT DC
CONTROL
MUX
SYSTEM CLOCK
P
HAS
E
A
CCUM
UL
AT
O
R
ACC
2
DDS CORE
12-BIT
I
DAC
12-BIT
Q DAC OR
CONTROL
DAC
I
Q
12
MUX
MU
X
MUX
SYSTEM
CLOCK
SYSTEM
CLOCK
48
14
BUS
12
14
17
48
AD9854
MODE SELECT
2
3
DE
M
UX
MU
X
MUX
12
INV
SINC
FILTER
12
I AND Q 12-BIT
AM MODULATION
0
06
36-
001
4× TO 20×
REF CLK
MULTIPLIER
INTERNAL
PROGRAMMABLE
UPDATE CLOCK
Figure 1.
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