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參數資料
| 型號： | AD9875-EB |
| 廠商： | Analog Devices, Inc. |
| 英文描述： | Broadband Modem Mixed-Signal Front End |
| 中文描述： | 寬帶調制解調器混合信號前端 |
| 文件頁數： | 23/24頁 |
| 文件大小： | 288K |
| 代理商： | AD9875-EB |
REV. 0
AD9875
–23–
Bit 3: Power-Down Interpolator at T xQUIE T Pin Low
Setting Bit 3 high enables the T xQUIET pin to shut off the
DAC output. If the bit is set to one, then pulling the T xQUIET
pin low will power down the interpolator filters. In most appli-
cations the interpolator filter will need to be flushed with zeros
before or after being powered down.
Bit 4 to Bit 7: Interpolation Filter Select
Bits 4 to 7 define the Interpolation filter characteristic and inter-
polation rate.
Bits 7:4;
0
×
2; Interpolation Bypass.
0
×
0; see T PC 1. 4
×
Interp, LPF.
0
×
1; see T PC 2. 2
×
Interp, LPF.
0
×
4; see T PC 3. 4
×
Interp, BPF, Adj image.
0
×
5; see T PC 4. 2
×
Interp, BPF, Adj image.
0
×
8; see T PC 5. 4
×
Interp, BPF, lower image.
0
×
C; see T PC 6. 4
×
Interp, BPF, upper image.
T he interpolation factor has a direct influence on the CLK -A
output frequency. When the transmit input data multiplexer is
enabled (10-bit mode):
f
CLK-A
= 2
×
f
DAC
/K
where
K
is the interpolation factor.
When the transmit input data multiplexer is disabled (5-/6-bit
mode):
f
CLK-A
=
f
DAC
/K
where
K
is the interpolation factor.
RE GIST E R 8—RE CE IVE R AND CLOCK OUT PUT
SE T T INGS
Bit 0: Rx Port Multiplexer Bypass
Setting this bit high bypasses the Rx port output multiplexer.
T his will output only the 6 MSBs of the ADC word. T his mode
enables ADC sampling rates above 55 MSPS.
Bit 1: Rx Port Width Five Bits
If the bit is set high, the Rx port data will be output in two
nibbles of five bits each (on pins Rx[5:1]). When this bit is low
(default), the most significant nibble will contain six bits and the
least significant nibble will have four bits. T he default mode
makes the AD9875 pin compatible with the AD9876.
Bit 2: Rx Port LS Nibble First
Reconfigures the AD9875 for a receive mode that expects less
significant bits before the most significant bits.
Bit 3: T hree-State Rx Port
T his bit sets the receive output Rx[5:0] into a high impedance
three-state mode. It allows for sharing the bus with other devices.
Bit 4, Bit 5: Disable CLK -A, Disable CLK -B
Setting Bit 4 or Bit 5 stops CLK -A or CLK -B respectively, from
toggling. T he output is held to a logic 0 level.
Bit 4, Bit 5: Disable CLK -A, Disable CLK -B
Setting Bit 4 or Bit 5 fixes CLK -A or CLK -B to a low output
level, respectively.
Bit 6: CLK -A Output Invert
Setting Bit 6 high inverts the CLK -A output signal.
Bit 7: CLK -B Output Invert
Setting this bit high inverts the CLK -B output signal. T his effec-
tively changes the timing of the Rx[5:0] and RxSYNC signals from
rising edge triggered to falling edge triggered with respect to the
CLK -B signal.
RE GIST E R F, DIE RE VISION
T his register stores the die revision of the chip. It is a read-
only register.
PCB DE SIGN CONSIDE RAT IONS
Although the AD9875 is a mixed-signal device, the part should
be treated as an analog component. T he digital circuitry on-chip
has been specially designed to minimize the impact that the
digital switching noise will have on the operation of the analog
circuits. Following the power, grounding and layout recommen-
dations in this section will help you get the best performance
from the MxFE.
Component Placement
If the three following guidelines of component placement are
followed, chances for getting the best performance from the
MxFE
are greatly increased. First, manage the path of return
currents flowing in the ground plane so that high frequency
switching currents from the digital circuits do not flow on the
ground plane under the MxFE or analog circuits. Second, keep
noisy digital signal paths and sensitive receive signal paths as
short as possible. T hird, keep digital (noise generating) and
analog (noise susceptible) circuits as far away from each other
as possible.
In order to best manage the return currents, pure digital circuits
that generate high switching currents should be closest to the
power supply entry. T his will keep the highest frequency return
current paths short, and prevent them from traveling over the
sensitive MxFE and analog portions of the ground plane. Also,
these circuits should be generously bypassed at each device
which will further reduce the high frequency ground currents.
T he MxFE should be placed adjacent to the digital circuits,
such that the ground return currents from the digital sections
will not flow in the ground plane under the MxFE. T he analog
circuits should be placed furthest from the power supply.
T he AD9875 has several pins which are used to decouple sensi-
tive internal nodes. T hese pins are REFIO, REFB, and REFT .
T he decoupling capacitors connected to these points should
have low ESR and ESL. T hese capacitors should be placed as
close to the MxFE as possible and be connected directly to the
analog ground plane.
T he resistor connected to the FSADJ pin should also be placed
close to the device and connected directly to the analog ground plane.
Power Planes and Decoupling
T he AD9875 evaluation board demonstrates a good power supply
distribution and decoupling strategy. T he board has four layers;
two signal layers, one ground plane and one power plane. T he
power plane is split into a 3VDD section used for the 3 V digital
logic circuits, a DVDD section used to supply the digital supply
pins of the AD9875, an AVDD section used to supply the
analog supply pins of the AD9875, and a VANLG section that
supplies the higher voltage analog components on the board.
T he 3VDD section will typically have the highest frequency
currents on the power plane and should be kept the furthest
from the MxFE and analog sections of the board. T he DVDD
portion of the plane brings the current used to power the digital
portion of the MxFE to the device. T his should be treated
similarly to the 3VDD power plane and be kept from going
underneath the MxFE or analog components. T he MxFE
should largely sit on the AVDD portion of the power plane.
相關PDF資料 |
PDF描述 |
|---|---|
| AD9875BST | Broadband Modem Mixed-Signal Front End |
| AD9876 | Broadband Modem Mixed-Signal Front End |
| AD9876-EB | Broadband Modem Mixed-Signal Front End |
| AD9876BST | Broadband Modem Mixed-Signal Front End |
| AD9876BSTRL | Broadband Modem Mixed-Signal Front End |
相關代理商/技術參數 |
參數描述 |
|---|---|
| AD9876 | 制造商:AD 制造商全稱:Analog Devices 功能描述:Broadband Modem Mixed-Signal Front End |
| AD9876ABST | 制造商:Rochester Electronics LLC 功能描述:12B BROADBAND MODEM MXFE CONVERTER - Tape and Reel 制造商:Analog Devices 功能描述: |
| AD9876ABSTRL | 制造商:Rochester Electronics LLC 功能描述:12B BROADBAND MODEM MXFE CONVERTER - Tape and Reel 制造商:Analog Devices 功能描述: |
| AD9876BST | 制造商:Analog Devices 功能描述:Modem Chip Single 48-Pin LQFP 制造商:Rochester Electronics LLC 功能描述:12B BROADBAND MODEM MXFE CONVERTER - Bulk |
| AD9876BSTRL | 制造商:Rochester Electronics LLC 功能描述:- Tape and Reel |
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