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參數(shù)資料
| 型號： | AD9942BBCZ |
| 廠商： | ANALOG DEVICES INC |
| 元件分類： | 消費家電 |
| 英文描述： | Dual-Channel, 14-Bit CCD Signal Processor with Precision Timing⑩ Core |
| 中文描述： | SPECIALTY CONSUMER CIRCUIT, PBGA100 |
| 封裝： | 9 X 9 MM, LEAD FREE, MO-205AB, CSPBGA-100 |
| 文件頁數(shù)： | 27/36頁 |
| 文件大小： | 452K |
| 代理商： | AD9942BBCZ |
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AD9942
CHANNEL A AND CHANNEL B ANALOG FRONT END OPERATION
The AD9942 signal processing chain is shown in Figure 28.
Each processing step is essential for achieving a high quality
image from the raw CCD pixel data.
Rev. A | Page 27 of 36
DC RESTORE
To reduce the large dc offset of the CCD output signal, a dc
restore circuit is used with an external 0.1 μF series coupling
capacitor. This restores the dc level of the CCDIN_X signal to
approximately 1.5 V to be compatible with the 3 V supply
voltage of the AD9942.
CORRELATED DOUBLE SAMPLER
The CDS circuit samples each CCD pixel twice to extract the
video information and reject low frequency noise. The timing
shown in Figure 17 illustrates how the two internally generated
CDS clocks, SHP and SHD, are used to sample the reference
level and the CCD signal level, respectively. The placement of
the SHP and SHD sampling edges is determined by the setting
of the SAMPCONTROL register located at Address 0x63.
Placement of these two clock signals is critical for achieving the
best performance from the CCD.
0
CCDIN_X
DIGITAL
FILTER
CLPOB
DC RESTORE
OPTICAL BLACK
CLAMP
ADC
DAC
8
CDS
INTERNAL
V
REF
2V FULL SCALE
0dB ~ 18dB
SHP
SHD
VGA1
1.5V
OUTPUT
DATA
LATCH
REFT_X
REFB_X
DOUT
PHASE
PBLK
1.0V
2.0V
DOUT
AD9942
1.0μF 1.0μF
1.0μF
VGA GAIN
REGISTERS
CLAMP LEVEL
REGISTER
14
CLPOB PBLK
V-H
TIMING
GENERATION
SHP
SHD
DOUT
PHASE
PRECISION
GETIMING
Figure 28. Channel A and Channel B Analog Front End Functional Block Diagram
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| AD9942BBCZRL | Dual-Channel, 14-Bit CCD Signal Processor with Precision Timing⑩ Core |
| AD9943 | Label Printer Tape RoHS Compliant: NA |
| AD9944 | Complete 10-Bit and 12-Bit, 25 MHz CCD Signal Processors |
| AD9943KCPZRL | Complete 10-Bit and 12-Bit, 25 MHz CCD Signal Processors |
| AD9944KCP | Complete 10-Bit and 12-Bit, 25 MHz CCD Signal Processors |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| AD9942BBCZRL | 功能描述:IC PROCESSOR SGNL 14B 100CSPBGA RoHS:是 類別:集成電路 (IC) >> 專用 IC 系列:- 產(chǎn)品培訓模塊:Lead (SnPb) Finish for COTS Obsolescence Mitigation Program 標準包裝:1 系列:- 類型:調(diào)幀器 應(yīng)用:數(shù)據(jù)傳輸 安裝類型:表面貼裝 封裝/外殼:400-BBGA 供應(yīng)商設(shè)備封裝:400-PBGA（27x27） 包裝:散裝 |
| AD9943 | 制造商:AD 制造商全稱:Analog Devices 功能描述:Complete 10-Bit and 12-Bit, 25 MHz CCD Signal Processors |
| AD9943KCP | 制造商:Analog Devices 功能描述:AFE Video 1ADC 10-Bit 3V 32-Pin LFCSP EP 制造商:Rochester Electronics LLC 功能描述:10 BIT 25 MHZ LOW COST ANALOG FRONT END - Bulk |
| AD9943KCPRL | 制造商:Analog Devices 功能描述:AFE Video 1ADC 10-Bit 3V 32-Pin LFCSP EP T/R |
| AD9943KCPZ | 功能描述:IC CCD SIGNAL PROCESSOR 32-LFCSP RoHS:是 類別:集成電路 (IC) >> 接口 - 傳感器和探測器接口 系列:- 其它有關(guān)文件:Automotive Product Guide 產(chǎn)品培訓模塊:Lead (SnPb) Finish for COTS Obsolescence Mitigation Program 標準包裝:74 系列:- 類型:觸控式傳感器 輸入類型:數(shù)字 輸出類型:數(shù)字 接口:JTAG，串行 電流 - 電源:100µA 安裝類型:表面貼裝 封裝/外殼:20-TSSOP（0.173"，4.40mm 寬） 供應(yīng)商設(shè)備封裝:20-TSSOP 包裝:管件 |
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