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參數資料
型號: AD9948KCP
廠商: ANALOG DEVICES INC
元件分類: 消費家電
英文描述: 10-Bit CCD Signal Processor with Precision Timing⑩ Core
中文描述: SPECIALTY CONSUMER CIRCUIT, QCC40
封裝: 6 X 6 MM, MO-220-VJJD-2, LFCSP-40
文件頁數: 16/28頁
文件大小: 539K
代理商: AD9948KCP
REV. 0
–16–
AD9948
HORIZONTAL CLAMPING AND BLANKING
The AD9948’s horizontal clamping and blanking pulses are
fully programmable to suit a variety of applications. Individual
sequences are defined for each signal, which are then organized
into multiple regions during image readout. This allows the dark
pixel clamping and blanking patterns to be changed at each
stage of the readout to accommodate different image transfer
timing and high speed line shifts.
Individual CLPOB and PBLK Sequences
The AFE horizontal timing consists of CLPOB and PBLK, as
shown in Figure 8. These two signals are independently pro-
grammed using the parameters shown in Table XII. The start
polarity, first toggle position, and second toggle position are
fully programmable for each signal. The CLPOB and PBLK
signals are active low, and should be programmed accordingly.
Up to four individual sequences can be created for each signal.
Individual HBLK Sequences
The HBLK programmable timing shown in Figure 9 is similar
to CLPOB and PBLK. However, there is no start polarity con-
trol. Only the toggle positions are used to designate the start and
the stop positions of the blanking period. Additionally, there is a
polarity control, HBLKMASK, which designates the polarity of
the horizontal clock signals H1–H4 during the blanking period.
Setting HBLKMASK high will set H1 = H3 = low and H2 =
H4 = high during the blanking, as shown in Figure 10. Up to
four individual sequences are available for HBLK.
(3)
(2)
(1)
HD
CLPOB
PBLK
. . .
PROGRAMMABLE SETTINGS:
1. START POLARITY (CLAMP AND BLANK REGION ARE ACTIVE LOW)
2. FIRST TOGGLE POSITION
3. SECOND TOGGLE POSITION
. . .
ACTIVE
ACTIVE
Figure 8. Clamp and Preblank Pulse Placement
(2)
(1)
HD
HBLK
. . .
PROGRAMMABLE SETTINGS:
1. FIRST TOGGLE POSITION = START OF BLANKING
2. SECOND TOGGLE POSITION = END OF BLANKING
. . .
BLANK
BLANK
Figure 9. Horizontal Blanking (HBLK) Pulse Placement
Table XII. CLPOB and PBLK Individual Sequence Parameters
Parameter
Length
Range
Description
Polarity
Toggle Position 1
Toggle Position 2
1b
12b
12b
High/Low
0–4095 Pixel Location
0–4095 Pixel Location
Starting Polarity of Clamp and PBLK Pulses for Sequences 0–3.
First Toggle Position within the Line for Sequences 0–3.
Second Toggle Position within the Line for Sequences 0–3.
Table XIII. HBLK Individual Sequence Parameters
Parameter
Length
Range
Description
HBLKMASK
Toggle Position 1
Toggle Position 2
Toggle Position 3
Toggle Position 4
Toggle Position 5
Toggle Position 6
1b
12b
12b
12b
12b
12b
12b
High/Low
0–4095 Pixel Location
0–4095 Pixel Location
0–4095 Pixel Location
0–4095 Pixel Location
0–4095 Pixel Location
0–4095 Pixel Location
Masking Polarity for H1 for Sequences 0–3 (0 = H1 Low, 1 = H1 High).
First Toggle Position within the Line for Sequences 0–3.
Second Toggle Position within the Line for Sequences 0–3.
Third Toggle Position within the Line for Sequences 0–3.
Fourth Toggle Position within the Line for Sequences 0–3.
Fifth Toggle Position within the Line for Sequences 0–3.
Sixth Toggle Position within the Line for Sequences 0–3.
相關PDF資料
PDF描述
AD9948KCPRL 10-Bit CCD Signal Processor with Precision Timing⑩ Core
AD9949KCP 12-Bit CCD Signal Processor with Precision Timing Core
AD9949 12-Bit CCD Signal Processor with Precision Timing Core
AD9949KCPZRL 12-Bit CCD Signal Processor with Precision Timing Core
AD9949KCPRL 12-Bit CCD Signal Processor with Precision Timing Core
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