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參數資料
| 型號： | AD9949 |
| 廠商： | Analog Devices, Inc. |
| 英文描述： | 12-Bit CCD Signal Processor with Precision Timing Core |
| 中文描述： | 12位CCD信號處理器核心的精密計時 |
| 文件頁數： | 23/36頁 |
| 文件大小： | 707K |
| 代理商： | AD9949 |
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AD9949
GENERATING SPECIAL HBLK PATTERNS
Six toggle positions are available for HBLK. Normally, only two
of the toggle positions are used to generate the standard HBLK
interval. However, the additional toggle positions may be used
to generate special HBLK patterns, as shown in Figure 24. The
pattern in this example uses all six toggle positions to generate
two extra groups of pulses during the HBLK interval. By
changing the toggle positions, different patterns can be created.
Rev. B | Page 23 of 36
HORIZONTAL SEQUENCE CONTROL
The AD9949 uses sequence change positions (SCP) and
sequence pointers (SPTR) to organize the individual horizontal
sequences. Up to four SCPs are available to divide the readout
into four separate regions, as shown in Figure 25. The SCP0 is
always hard-coded to Line 0, and SCP1 to SCP3 are register
programmable. During each region bounded by the SCP, the
SPTR registers designate which sequence is used by each signal.
CLPOB, PBLK, and HBLK each have a separate set of SCPs. For
example, CLPOBSCP1 defines Region 0 for CLPOB, and in that
region any of the four individual CLPOB sequences may be
selected with the CLPOBSPTR register. The next SCP defines a
new region and in that region, each signal can be assigned to a
different individual sequence. The sequence control registers
are summarized in Table 20.
EXTERNAL HBLK SIGNAL
The AD9949 can also be used with an external HBLK signal.
Setting the HBLKDIR register (Address 0×40) to high disables
the internal HBLK signal generation. The polarity of the exter-
nal signal is specified using the HBLKPOL register, and the
masking polarity of H1 is specified using the HBLKMASK
register. Table 21 summarizes the register values when using an
external HBLK signal.
UP TO FOUR INDIVIDUAL HORIZONTAL CLAMP AND BLANKING REGIONS MAY BE
PROGRAMMED WITHIN A SINGLE FIELD, USING THE SEQUENCE CHANGE POSITIONS.
SEQUENCE CHANGE OF POSITION 1
SEQUENCE CHANGE OF POSITION 2
SEQUENCE CHANGE OF POSITION 3
SINGLE FIELD (1 VD INTERVAL)
CLAMP AND PBLK SEQUENCE REGION 0
SEQUENCE CHANGE OF POSITION 0
(V-COUNTER = 0)
CLAMP AND PBLK SEQUENCE REGION 3
CLAMP AND PBLK SEQUENCE REGION 2
CLAMP AND PBLK SEQUENCE REGION 1
0
Figure 25. Clamp and Blanking Sequence Flexibility
Table 21. External HBLK Register Parameters
Register
HBLKDIR
Length
1b
Range
High/Low
Description
Specifies HBLK Internally Generated or Externally Supplied.
1 = External.
External HBLK Active Polarity.
0 = Active Low.
1 = Active High.
External HBLK Masking Polarity.
0 = Mask H1 Low.
1 = Mask H1 High.
HBLKPOL
1b
High/Low
HBLKEXTMASK
1b
High/Low
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