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參數(shù)資料
| 型號： | AD9956YCPZ-REEL1 |
| 廠商： | Analog Devices, Inc. |
| 英文描述： | 2.7 GHz DDS-Based AgileRF |
| 中文描述： | 2.7千兆赫基于DDS的AgileRF |
| 文件頁數(shù)： | 1/32頁 |
| 文件大小： | 805K |
| 代理商： | AD9956YCPZ-REEL1 |
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2.7 GHz DDS-Based
Agile
RF
TM
Synthesizer
AD9956
FEATURES
Rev.
0
Information furnished by Analog Devices is believed to be accurate and reliable.
However, no responsibility is assumed by Analog Devices for its use, nor for any
infringements of patents or other rights of third parties that may result from its use.
Specifications subject to change without notice. No license is granted by implication
or otherwise under any patent or patent rights of Analog Devices. Trademarks and
registered trademarks are the property of their respective owners.
Tel: 781.329.4700Fax: 781.326.8703
400 MSPS internal DDS clock speed 48-bit frequency tuning word
14-bit programmable phase offset
Integrated 14-bit DAC
Excellent dynamic performance
Phase noise ≤ 135 dBc/Hz @ 1 KHz offset
80 dB SFDR @ 160 MHz (±100 KHz offset I
OUT
)
25 Mb/s write-speed serial I/O control
200 MHz phase frequency detector inputs
655 MHz programmable input dividers for the phase
frequency detector (÷M, ÷N) {M, N = 1..16} (bypassable)
Programmable RF divider (÷R) {R = 1, 2, 4, 8} (bypassable)
8 phase/frequency profiles
1.8 V supply for device operation
3.3 V supply for I/O and charge pump
Software controlled power-down
48-lead LFCSP package
Automatic linear frequency sweeping capability (in DDS)
Programmable charge pump current (up to 4 mA)
Phase modulation capability
Multichip synchronization
Dual-mode PLL lock detect
655 MHz CML-mode PECL-compliant driver
APPLICATIONS
Agile LO frequency synthesis
FM chirp source for radar and scanning systems
Automotive radars
Test and measurement equipment
Acousto-optic device drivers
FUNCTIONAL BLOCK DIAGRAM
FREQUENCY
ACCUMULATOR
PHASE
ACCUMULATOR
PHASE
OFFSET
PHASE
OFFSET
WORD
TIMING AND CONTROL LOGIC
PHASE TO
AMPLITUDE
CONVERSION
14
FTW
48
24
DAC
RF-DIVIDER
÷
R
FROM PLLOSC
3
PS<2:0> RESET I/O PORT
CHARGE
PUMP
SCALER
Φ
BUFFER
BUFFER
CP_OUT
CP_RSET
PLL_LOCK/SYNC_IN
I/O_UPDATE
SYNC_OUT
REFCLK
REFCLK
CML CLOCK DRIVER
DRV DRV DRV_RSET
DAC_RSET
IOUT
IOUT
SYNC_CLK
SYSCLK
DELTA
FREQUENCY
TUNING WORD
DELTA
FREQUENCY
RAMP RATE
SYSCLK
3
LOCK
DETECT
48
19
14
DDS CORE
SYSCLK
I/O_RESET
OSCILLATOR
16
CHARGE
PUMP
PLLREF/
PLLREF
PLLOSC/
PLLOSC
÷
N
÷
4
÷
M
0
Figure 1.
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| AD9956YCPZ-REEL7 | 功能描述:IC SYNTHESIZER 1.8V 48LFCSP RoHS:是 類別:集成電路 (IC) >> 接口 - 直接數(shù)字合成 (DDS) 系列:- 產(chǎn)品變化通告:Product Discontinuance 27/Oct/2011 標(biāo)準(zhǔn)包裝:2,500 系列:- 分辨率（位）:10 b 主 fclk:25MHz 調(diào)節(jié)字寬（位）:32 b 電源電壓:2.97 V ~ 5.5 V 工作溫度:-40°C ~ 85°C 安裝類型:表面貼裝 封裝/外殼:16-TSSOP（0.173"，4.40mm 寬） 供應(yīng)商設(shè)備封裝:16-TSSOP 包裝:帶卷 (TR) |
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| AD9957/PCBZ | 功能描述:BOARD EVAL AD9957 QUADRATURE MOD RoHS:是 類別:編程器，開發(fā)系統(tǒng) >> 評估演示板和套件 系列:AgileRF™ 標(biāo)準(zhǔn)包裝:1 系列:PSoC® 主要目的:電源管理，熱管理 嵌入式:- 已用 IC / 零件:- 主要屬性:- 次要屬性:- 已供物品:板，CD，電源 |
| AD9957_07 | 制造商:AD 制造商全稱:Analog Devices 功能描述:1 GSPS Quadrature Digital Upconverter with 18-Bit IQ Data Path and 14-Bit DAC |
| AD9957BCPZ | 制造商:Analog Devices 功能描述:GSPS QUADRATURE DIGITAL UPCONVERTER W/18-BIT IQ DATA PATH - Trays |
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