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參數資料
| 型號： | AD9956YCPZ1 |
| 廠商： | Analog Devices, Inc. |
| 英文描述： | 2.7 GHz DDS-Based AgileRF |
| 中文描述： | 2.7千兆赫基于DDS的AgileRF |
| 文件頁數： | 12/32頁 |
| 文件大小： | 805K |
| 代理商： | AD9956YCPZ1 |
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AD9956
Table 3. 48-Lead LFCSP Pin Function Description
Pin No.
Mnemonic
1, 3, 8, 26, 30,
34, 37, 43, 49
2, 4, 7, 27, 31,
38, 44, 48
5
IOUT
6
IOUT
9
I/O_RESET
Rev. 0 | Page 12 of 32
Description
Analog Ground.
AGND
AVDD
Analog Core Supply (1.8 V).
DAC Analog Output.
DAC Analog Complementary Output.
Resets the serial port when synchronization is lost in communications but does not reset the de-
vice itself (ACTIVE HIGH). When not being used, this pin should be forced low, because it floats to
the threshold value.
Master RESET. Clears all accumulators and returns all registers to their default values (ACTIVE
HIGH).
Digital Core Supply (1.8 V).
Digital Ground.
Serial Data Output. Used only when device is programmed for 3-wire serial data mode.
Serial Data I/O. When the part is programmed for 3-wire serial data mode, this is input only; in
2-wire mode, it serves as both the input and output.
Serial Data Clock. Provides the clock signal for the serial data port.
Active Low Signal That Enables Shared Serial Busses. When brought high, the serial port ignores
the serial data clocks.
Digital Interface Supply (3.3 V).
Synchronization Clock Output.
Bidirectional Dual Function Pin. Depending on device programming, it is either the DDS’ synchro-
nization input (allows alignment of multiple subclocks) or the PLL lock detect output signal.
This input pin, when set high, transfers the data from the I/O buffers to the internal registers on the
rising edge of the internal SYNC_CLK, which can be observed on SYNC_OUT.
Profile Select Pins. Specify one of eight frequency tuning word/phase offset word profiles. In linear
sweep mode, PS0 determines the state of the sweep. In linear sweep no dwell mode, PS0 is a trig-
ger that initiates the sweep. PS1 and PS2 have no function during linear sweep mode or linear
sweep no dwell mode.
RF Divider and DDS REFCLK Complementary Input.
RF Divider and DDS REFCLK Input.
CML Driver Complementary Output.
CML Driver Output.
Charge Pump Supply Pin (3.3 V). To minimize noise on the charge pump, isolate this supply from
DVDD_I/O.
Charge Pump Output.
Phase Frequency Detector Reference Input.
Phase Frequency Detector Reference Complementary Input.
Phase Frequency Detector Oscillator (Feedback) Complementary Input.
Phase Frequency Detector Oscillator (Feedback) Input.
Charge Pump Current Set (Program Charge Pump Current with a Resistor to AGND).
CML Driver Output Current Set (Program CML Output Current with a Resistor to AGND).
DAC Output Current Set (Program DAC Output Current with a Resistor to AGND).
10
RESET
11, 25
12, 24
13
14
DVDD
DGND
SDO
SDI/O
15
16
SCLK
CS
17
18
19
DVDD_I/O
SYNC_OUT
PLL_LOCK/SYNC_IN
20
I/O_UPDATE
21 to 23
PS0 to PS2
28
29
32
33
35
REFCLK
REFCLK
DRV
DRV
CP_VDD
36
39
40
41
42
45
46
47
CP_OUT
PLLREF
PLLREF
PLLOSC
PLLOSC
CP_RSET
DRV_RSET
DAC_RSET
Note that the exposed paddle on this package is an electrical connection (Pin 49) as well as a thermal enhancement. In order for the
device to function properly, the paddle MUST be attached to analog ground.
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相關代理商/技術參數 |
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| AD9956YCPZ-REEL1 | 制造商:AD 制造商全稱:Analog Devices 功能描述:2.7 GHz DDS-Based AgileRF |
| AD9956YCPZ-REEL7 | 功能描述:IC SYNTHESIZER 1.8V 48LFCSP RoHS:是 類別:集成電路 (IC) >> 接口 - 直接數字合成 (DDS) 系列:- 產品變化通告:Product Discontinuance 27/Oct/2011 標準包裝:2,500 系列:- 分辨率（位）:10 b 主 fclk:25MHz 調節字寬（位）:32 b 電源電壓:2.97 V ~ 5.5 V 工作溫度:-40°C ~ 85°C 安裝類型:表面貼裝 封裝/外殼:16-TSSOP（0.173"，4.40mm 寬） 供應商設備封裝:16-TSSOP 包裝:帶卷 (TR) |
| AD9957 | 制造商:AD 制造商全稱:Analog Devices 功能描述:1 GSPS Quadrature Digital Upconverter with 18-Bit IQ Data Path and 14-Bit DAC |
| AD9957/PCBZ | 功能描述:BOARD EVAL AD9957 QUADRATURE MOD RoHS:是 類別:編程器，開發系統 >> 評估演示板和套件 系列:AgileRF™ 標準包裝:1 系列:PSoC® 主要目的:電源管理，熱管理 嵌入式:- 已用 IC / 零件:- 主要屬性:- 次要屬性:- 已供物品:板，CD，電源 |
| AD9957_07 | 制造商:AD 制造商全稱:Analog Devices 功能描述:1 GSPS Quadrature Digital Upconverter with 18-Bit IQ Data Path and 14-Bit DAC |
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