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參數資料
| 型號： | ADC100CA |
| 廠商： | Electronic Theatre Controls, Inc. |
| 英文描述： | Low-Voltage High-Speed Quadruple Differential Line Receiver 16-SOIC 0 to 70 |
| 中文描述： | 精密集成22位A / D轉換 |
| 文件頁數： | 5/7頁 |
| 文件大小： | 127K |
| 代理商： | ADC100CA |
CONNECTING THE ADC100
POWER SUPPLIES
The power supply lines are connected to pins 4-7.
Pin 4 is -15V, pin 5 is +15v, pin 6 is +5V and pin 7 is
GND.
OUTPUT DATA LINES
The output data is available in byte form on pins
13-20. Pin 20 is the Most Significant Bit and pin 13
the Least Significant Bit. The data lines go to a high
impedance state when the Output Enable line is at a
logic one level.
OUTPUT ENABLE (PIN 21)
Data is placed on the Output Data Lines by a logic
zero on this line.
CONVERT (Pin22)
This line is used to initiate a conversion cycle and
to retrieve the output data. The status lines indicate
which function will be executed. The first pulse
(transition from logic one to logic zero) starts the
conversion cycle. Two subsequent pulses are used
to place the lower two bytes on the Output Data
Lines.
Conversion in progress.
Conversion complete. MSB in output.
Middle byte in output register.
LSB in output. Ready for next conversion.
0 0
0 1
1 0
1 1
S
1
S
0
AUTO-ZERO / RESET (Pin 29)
A logic zero on this input will autozero the ADC150-
3 by internally connecting the analog high to analog
low. Since the μP is reset the status lines S1 and
S0 are tristate before going to the low position. The
status lines will remain low until the autozero is
complete.
INTEGRATION CAPACITOR (Pin 34, 35)
A .68 μF polystyrene capacitor must be connected
to these pins. Lead length should be as short as
possible and not exceed 2".
ANALOG INPUTS (Pin 39, 40)
Both analog inputs are buffered by op-amps and
have a common mode rejection of approximately
80dB. min. To maintain the full accuracy at the
ADC it is recommended to keep the input to analog
common to less than 0.1VDC.
OUTPUT DATA REPRESENTATION
The output data is represented in BOB (Bipolar Offset Binary)
format. One LSB is scaled to be exactly 5mV. The table below
shows the output data codes for zero and plus-minus full scale
input voltage.
Input Voltage
Output Data
Middle Byte
00
00
FF
High Byte
00
20
3F
Low Byte
00
00
FF
-10.485760 V
0.0 V
+10.485755 V
STATUS LINES (Pins 23, 24)
These lines indicate the present state of the ADC. When the Convert line receives the first pulse in a
conversion cycle the Status Lines go to logic zero, indicating that a conversion cycle is in progress. When
the conversion is complete the microprocessor places the MSB of the output data in the output buffer and
then raises S
to a logic one, indicating that the MSB at the output data is available in the output buffer.
When the Convert Line is pulsed again the middle byte of the output data is placed in that output buffer and
S
changes to logic one and S
to logic zero. The third pulse places the LSB of the output data in the buffer
and both status lines go to the logic one. The converter is now ready for the next conversion cycle.
The table below shows a summary of the status code.
ADC100DS REV. E MAR 00
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