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參數資料
| 型號： | ADCMP551 |
| 廠商： | Analog Devices, Inc. |
| 英文描述： | Single Supply High Speed PECL Comparators |
| 中文描述： | 單電源高速PECL的比較 |
| 文件頁數： | 10/14頁 |
| 文件大小： | 522K |
| 代理商： | ADCMP551 |
ADCMP551/ADCMP552/ADCMP553
Preliminary Technical Data
TIMING INFORMATION
Rev. PrB | Page 10 of 14
50%
50%
V
REF
± V
OS
50%
DIFFERENTIAL
INPUT VOLTAGE
LATCH ENABLE
Q OUTPUT
Q OUTPUT
LATCH ENABLE
t
H
t
PDL
t
PDH
t
PLOH
t
PLOL
t
R
t
F
V
IN
V
OD
t
S
t
PL
0
Figure 16. System Timing Diagram
Figure 16 shows the compare and latch features of the ADCMP55x family. Table 4 describes the terms in the diagram.
Table 4. Timing Descriptions
Symbol
Timing
t
PDH
Input to Output High Delay
Description
Propagation delay measured from the time the input signal crosses the reference (± the
input offset voltage) to the 50% point of an output low-to-high transition
Propagation delay measured from the time the input signal crosses the reference (± the
input offset voltage) to the 50% point of an output high-to-low transition
Propagation delay measured from the 50% point of the latch enable signal low-to-high
transition to the 50% point of an output low-to-high transition
Propagation delay measured from the 50% point of the latch enable signal low-to-high
transition to the 50% point of an output high-to-low transition
Minimum time after the negative transition of the latch enable signal that the input signal
must remain unchanged to be acquired and held at the outputs
Minimum time the latch enable signal must be high to acquire an input signal change
Minimum time before the negative transition of the latch enable signal that an input
signal change must be present to be acquired and held at the outputs
Amount of time required to transition from a low to a high output as measured at the
20% and 80% points
Amount of time required to transition from a high to a low output as measured at the
20% and 80% points
Difference between the differential input and reference input voltages
t
PDL
Input to Output Low Delay
t
PLOH
Latch Enable to Output High Delay
t
PLOL
Latch Enable to Output Low Delay
t
H
Minimum Hold Time
t
PL
t
S
Minimum Latch Enable Pulse Width
Minimum Setup Time
t
R
Output Rise Time
t
F
Output Fall Time
V
OD
Voltage Overdrive
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| ADCMP551BRQ | Single Supply High Speed PECL Comparators |
| ADCMP552 | Single Supply High Speed PECL Comparators |
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| ADCMP553 | Single Supply High Speed PECL Comparators |
| ADCMP553BRM | Single Supply High Speed PECL Comparators |
相關代理商/技術參數 |
參數描述 |
|---|---|
| ADCMP551_0410 | 制造商:AD 制造商全稱:Analog Devices 功能描述:Single-Supply, High Speed PECL/LVPECL Comparators |
| ADCMP551_13 | 制造商:AD 制造商全稱:Analog Devices 功能描述:Single Supply High Speed PECL/LVPECL Comparators |
| ADCMP551BRQ | 功能描述:IC COMPARATOR PECL/LVPECL 16QSOP RoHS:否 類別:集成電路 (IC) >> 線性 - 比較器 系列:- 產品培訓模塊:Lead (SnPb) Finish for COTS Obsolescence Mitigation Program 標準包裝:2,500 系列:- 類型:通用 元件數:1 輸出類型:CMOS，推挽式，滿擺幅，TTL 電壓 - 電源，單路/雙路(±):2.5 V ~ 5.5 V，±1.25 V ~ 2.75 V 電壓 - 輸入偏移（最小值）:5mV @ 5.5V 電流 - 輸入偏壓（最小值）:1pA @ 5.5V 電流 - 輸出（標準）:- 電流 - 靜態（最大值）:24µA CMRR, PSRR（標準）:80dB CMRR，80dB PSRR 傳輸延遲（最大）:450ns 磁滯:±3mV 工作溫度:-40°C ~ 85°C 封裝/外殼:6-WFBGA，CSPBGA 安裝類型:表面貼裝 包裝:管件 其它名稱:Q3554586 |
| ADCMP551BRQZ | 功能描述:IC COMPARATOR PECL/LVPECL 16QSOP RoHS:是 類別:集成電路 (IC) >> 線性 - 比較器 系列:- 標準包裝:1 系列:- 類型:通用 元件數:1 輸出類型:CMOS，開路集電極，TTL 電壓 - 電源，單路/雙路(±):2.7 V ~ 5.5 V 電壓 - 輸入偏移（最小值）:7mV @ 5V 電流 - 輸入偏壓（最小值）:0.25µA @ 5V 電流 - 輸出（標準）:84mA @ 5V 電流 - 靜態（最大值）:120µA CMRR, PSRR（標準）:- 傳輸延遲（最大）:600ns 磁滯:- 工作溫度:-40°C ~ 85°C 封裝/外殼:SC-74A，SOT-753 安裝類型:表面貼裝 包裝:剪切帶 (CT) 產品目錄頁面:1268 (CN2011-ZH PDF) 其它名稱:*LMV331M5*LMV331M5/NOPBLMV331M5CT |
| ADCMP551BRQZ-REEL7 | 功能描述:IC COMPARATOR PECL/LVPECL 16QSOP RoHS:是 類別:集成電路 (IC) >> 線性 - 比較器 系列:- 產品培訓模塊:Lead (SnPb) Finish for COTS Obsolescence Mitigation Program 標準包裝:2,500 系列:- 類型:通用 元件數:1 輸出類型:CMOS，推挽式，滿擺幅，TTL 電壓 - 電源，單路/雙路(±):2.5 V ~ 5.5 V，±1.25 V ~ 2.75 V 電壓 - 輸入偏移（最小值）:5mV @ 5.5V 電流 - 輸入偏壓（最小值）:1pA @ 5.5V 電流 - 輸出（標準）:- 電流 - 靜態（最大值）:24µA CMRR, PSRR（標準）:80dB CMRR，80dB PSRR 傳輸延遲（最大）:450ns 磁滯:±3mV 工作溫度:-40°C ~ 85°C 封裝/外殼:6-WFBGA，CSPBGA 安裝類型:表面貼裝 包裝:管件 其它名稱:Q3554586 |
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