- 您現在的位置：買賣IC網 > PDF目錄373976 > ADCMP564 (Analog Devices, Inc.) Dual High Speed ECL Comparators PDF資料下載
參數資料
| 型號： | ADCMP564 |
| 廠商： | Analog Devices, Inc. |
| 英文描述： | Dual High Speed ECL Comparators |
| 中文描述： | 雙高速ECL比較 |
| 文件頁數： | 6/16頁 |
| 文件大小： | 326K |
| 代理商： | ADCMP564 |
ADCMP563/ADCMP564
PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS
Rev. A | Page 6 of 16
0
ADCMP563
TOP VIEW
(Not to Scale)
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
–INA
+INA
QA
QA
GND
V
EE
LEA
LEA
–INB
+INB
QB
QB
GND
V
CC
LEB
LEB
0
ADCMP564
TOP VIEW
(Not to Scale)
1
2
3
4
5
6
7
8
9
10
20
19
18
17
16
15
14
13
12
11
–INA
QA
QA
GND
V
EE
LEA
LEA
GND
+INA
HYSA
–INB
QB
QB
GND
V
CC
LEB
LEB
GND
+INB
HYSB
Figure 4. ADCMP563 16-Lead QSOP Pin Configuration
Figure 5. ADCMP564 20-Lead QSOP Pin Configuration
Table 3. Pin Function Descriptions
Pin No.
ADCMP563
ADCMP564
1
1
2
Mnemonic
GND
QA
Function
Analog Ground.
One of two complementary outputs for Channel A. QA is logic high if the analog voltage at the
noninverting input is greater than the analog voltage at the inverting input (provided the
comparator is in compare mode). See the description of Pin LEA for more information.
One of two complementary outputs for Channel A. QA is logic low if the analog voltage at the
noninverting input is greater than the analog voltage at the inverting input (provided the
comparator is in compare mode). See the description of Pin LEA for more information.
Analog Ground.
One of two complementary inputs for Channel A Latch Enable. In compare mode (logic high),
the output tracks changes at the input of the comparator. In latch mode (logic low), the output
reflects the input state just prior to the comparator being placed in the latch mode. LEA must
be driven in conjunction with LEA. If left unconnected, the comparator defaults to compare
mode.
One of two complementary inputs for Channel A Latch Enable. In compare mode (logic low),
the output tracks changes at the input of the comparator. In latch mode (logic high), the
output reflects the input state just prior to the comparator being placed in the latch mode. LEA
must be driven in conjunction with LEA. If left unconnected, the comparator defaults to
compare mode.
Negative Supply Terminal.
Inverting Analog Input of the Differential Input Stage for Channel A. The inverting A input must
be driven in conjunction with the noninverting A input.
Noninverting Analog Input of the Differential Input Stage for Channel A. The noninverting A
input must be driven in conjunction with the inverting A input.
Programmable Hysteresis Input.
Programmable Hysteresis Input.
Noninverting Analog Input of the Differential Input Stage for Channel B. The noninverting B
input must be driven in conjunction with the inverting B input.
Inverting Analog Input of the Differential Input Stage for Channel B. The inverting B input must
be driven in conjunction with the noninverting B input.
Positive Supply Terminal.
One of two complementary inputs for Channel B Latch Enable. In compare mode (logic low),
the output tracks changes at the input of the comparator. In latch mode (logic high), the
output reflects the input state just prior to the comparator being placed in the latch mode. LEB
must be driven in conjunction with LEB. If left unconnected, the comparator defaults to
compare mode.
2
3
QA
3
4
4
5
GND
LEA
5
6
LEA
6
7
7
8
V
EE
INA
8
9
+INA
9
10
11
12
HYSA
HYSB
+INB
10
13
INB
11
12
14
15
V
CC
LEB
相關PDF資料 |
PDF描述 |
|---|---|
| ADCMP564BRQ | Dual High Speed ECL Comparators |
| ADCMP566 | Dual Ultrafast Voltage Comparator |
| ADCMP566BCP | Dual Ultrafast Voltage Comparator |
| ADCMP567 | Dual Ultrafast Voltage Comparator |
| ADCMP567BCP | Dual Ultrafast Voltage Comparator |
相關代理商/技術參數 |
參數描述 |
|---|---|
| ADCMP564BRQ | 功能描述:IC COMPARATOR ECL DUAL HS 20QSOP RoHS:否 類別:集成電路 (IC) >> 線性 - 比較器 系列:- 產品培訓模塊:Lead (SnPb) Finish for COTS Obsolescence Mitigation Program 標準包裝:2,500 系列:- 類型:通用 元件數:1 輸出類型:CMOS，推挽式，滿擺幅，TTL 電壓 - 電源，單路/雙路(±):2.5 V ~ 5.5 V，±1.25 V ~ 2.75 V 電壓 - 輸入偏移（最小值）:5mV @ 5.5V 電流 - 輸入偏壓（最小值）:1pA @ 5.5V 電流 - 輸出（標準）:- 電流 - 靜態（最大值）:24µA CMRR, PSRR（標準）:80dB CMRR，80dB PSRR 傳輸延遲（最大）:450ns 磁滯:±3mV 工作溫度:-40°C ~ 85°C 封裝/外殼:6-WFBGA，CSPBGA 安裝類型:表面貼裝 包裝:管件 其它名稱:Q3554586 |
| ADCMP564BRQZ | 功能描述:IC COMPARATOR ECL DUAL HS 20QSOP RoHS:是 類別:集成電路 (IC) >> 線性 - 比較器 系列:- 標準包裝:1 系列:- 類型:通用 元件數:1 輸出類型:CMOS，開路集電極，TTL 電壓 - 電源，單路/雙路(±):2.7 V ~ 5.5 V 電壓 - 輸入偏移（最小值）:7mV @ 5V 電流 - 輸入偏壓（最小值）:0.25µA @ 5V 電流 - 輸出（標準）:84mA @ 5V 電流 - 靜態（最大值）:120µA CMRR, PSRR（標準）:- 傳輸延遲（最大）:600ns 磁滯:- 工作溫度:-40°C ~ 85°C 封裝/外殼:SC-74A，SOT-753 安裝類型:表面貼裝 包裝:剪切帶 (CT) 產品目錄頁面:1268 (CN2011-ZH PDF) 其它名稱:*LMV331M5*LMV331M5/NOPBLMV331M5CT |
| ADCMP565 | 制造商:AD 制造商全稱:Analog Devices 功能描述:Dual Ultrafast Voltage Comparator |
| ADCMP565BP | 功能描述:IC COMP DUAL ULTRA-FAST 20-PLCC RoHS:否 類別:集成電路 (IC) >> 線性 - 比較器 系列:- 產品培訓模塊:Lead (SnPb) Finish for COTS Obsolescence Mitigation Program 標準包裝:2,500 系列:- 類型:通用 元件數:1 輸出類型:CMOS，推挽式，滿擺幅，TTL 電壓 - 電源，單路/雙路(±):2.5 V ~ 5.5 V，±1.25 V ~ 2.75 V 電壓 - 輸入偏移（最小值）:5mV @ 5.5V 電流 - 輸入偏壓（最小值）:1pA @ 5.5V 電流 - 輸出（標準）:- 電流 - 靜態（最大值）:24µA CMRR, PSRR（標準）:80dB CMRR，80dB PSRR 傳輸延遲（最大）:450ns 磁滯:±3mV 工作溫度:-40°C ~ 85°C 封裝/外殼:6-WFBGA，CSPBGA 安裝類型:表面貼裝 包裝:管件 其它名稱:Q3554586 |
| ADCMP565BPZ | 功能描述:IC COMP DUAL ULTRA-FAST 20-PLCC RoHS:是 類別:集成電路 (IC) >> 線性 - 比較器 系列:- 標準包裝:1 系列:- 類型:通用 元件數:1 輸出類型:CMOS，開路集電極，TTL 電壓 - 電源，單路/雙路(±):2.7 V ~ 5.5 V 電壓 - 輸入偏移（最小值）:7mV @ 5V 電流 - 輸入偏壓（最小值）:0.25µA @ 5V 電流 - 輸出（標準）:84mA @ 5V 電流 - 靜態（最大值）:120µA CMRR, PSRR（標準）:- 傳輸延遲（最大）:600ns 磁滯:- 工作溫度:-40°C ~ 85°C 封裝/外殼:SC-74A，SOT-753 安裝類型:表面貼裝 包裝:剪切帶 (CT) 產品目錄頁面:1268 (CN2011-ZH PDF) 其它名稱:*LMV331M5*LMV331M5/NOPBLMV331M5CT |
發布緊急采購，3分鐘左右您將得到回復。