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參數(shù)資料
| 型號(hào)： | ADCMP567 |
| 廠商： | Analog Devices, Inc. |
| 英文描述： | Dual Ultrafast Voltage Comparator |
| 中文描述： | 雙超高速電壓比較器 |
| 文件頁(yè)數(shù)： | 8/17頁(yè) |
| 文件大?。?/td> | 362K |
| 代理商： | ADCMP567 |
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ADCMP567
TIMING INFORMATION
Rev. 0 | Page 8 of 16
50%
50%
V
REF
± V
OS
50%
DIFFERENTIAL
INPUT VOLTAGE
LATCH ENABLE
Q OUTPUT
Q OUTPUT
LATCH ENABLE
t
H
t
PDL
t
PDH
t
PLOH
t
PLOL
t
R
t
F
V
IN
V
OD
t
S
t
PL
03633-0-003
Figure 3. System Timing Diagram
The timing diagram in Figure 3 shows the ADCMP567 compare
and latch features. Table 4 describes the terms in the diagram.
Table 4. Timing Descriptions
Symbol
Timing
Description
t
PDH
Input to output
high delay
the time the input signal crosses
the reference (± the input offset
voltage) to the 50% point of an
output low-to-high transition
t
PDL
Input to output
low delay
the time the input signal crosses
the reference (± the input offset
voltage) to the 50% point of an
output high-to-low transition
t
PLOH
Latch enable
to output high
delay
signal low-to-high transition to
the 50% point of an output low-
to-high transition
t
PLOL
Latch enable
to output low
delay
signal low-to-high transition to
the 50% point of an output high-
to-low transition
Propagation delay measured from
Propagation delay measured from
Propagation delay measured from
the 50% point of the Latch Enable
Propagation delay measured from
the 50% point of the Latch Enable
Symbol
t
H
Timing
Minimum
hold time
Description
Minimum time after the negative
transition of the Latch Enable
signal that the input signal must
remain unchanged to be acquired
and held at the outputs
Minimum time that the Latch
Enable signal must be high to
acquire an input signal change
Minimum time before the
negative transition of the Latch
Enable signal that an input signal
change must be present to be
acquired and held at the outputs
Amount of time required to
transition from a low to a high
output as measured at the 20%
and 80% points
Amount of time required to
transition from a high to a low
output as measured at the 20%
and 80% points
Difference between the
differential input and reference
input voltages
t
PL
Minimum
latch enable
pulsewidth
Minimum
setup time
t
S
t
R
Output rise
time
t
F
Output fall
time
V
OD
Voltage
overdrive
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相關(guān)代理商/技術(shù)參數(shù) |
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| ADCMP567BCP | 制造商:Analog Devices 功能描述:Comparator Dual -5.45V/5.25V 32-Pin LFCSP EP 制造商:Analog Devices 功能描述:IC COMPARATOR HIGH SPEED |
| ADCMP567BCPZ | 功能描述:IC COMP DUAL ULTRA-FAST 32LFCSP RoHS:是 類(lèi)別:集成電路 (IC) >> 線性 - 比較器 系列:- 標(biāo)準(zhǔn)包裝:1 系列:- 類(lèi)型:通用 元件數(shù):1 輸出類(lèi)型:CMOS，開(kāi)路集電極，TTL 電壓 - 電源，單路/雙路(±):2.7 V ~ 5.5 V 電壓 - 輸入偏移（最小值）:7mV @ 5V 電流 - 輸入偏壓（最小值）:0.25µA @ 5V 電流 - 輸出（標(biāo)準(zhǔn)）:84mA @ 5V 電流 - 靜態(tài)（最大值）:120µA CMRR, PSRR（標(biāo)準(zhǔn)）:- 傳輸延遲（最大）:600ns 磁滯:- 工作溫度:-40°C ~ 85°C 封裝/外殼:SC-74A，SOT-753 安裝類(lèi)型:表面貼裝 包裝:剪切帶 (CT) 產(chǎn)品目錄頁(yè)面:1268 (CN2011-ZH PDF) 其它名稱(chēng):*LMV331M5*LMV331M5/NOPBLMV331M5CT |
| ADCMP572 | 制造商:AD 制造商全稱(chēng):Analog Devices 功能描述:Ultrafast 3.3 V Single-Supply Comparators |
| ADCMP572_05 | 制造商:AD 制造商全稱(chēng):Analog Devices 功能描述:Ultrafast 3.3 V/5 V Single-Supply SiGe Comparators |
| ADCMP572BCP | 制造商:AD 制造商全稱(chēng):Analog Devices 功能描述:Ultrafast 3.3 V Single-Supply Comparators |
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