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參數資料
| 型號： | ADCMP572 |
| 廠商： | Analog Devices, Inc. |
| 英文描述： | Ultrafast 3.3 V Single-Supply Comparators |
| 中文描述： | 超快3.3 V單電源比較 |
| 文件頁數： | 13/16頁 |
| 文件大小： | 412K |
| 代理商： | ADCMP572 |
Preliminary Technical Data
ADCMP572/ADCMP573
TIMING INFORMATION
Figure 25 illustrates the ADCMP572/ADCMP573 compare and
latch timing relationships. Table 4 provides definitions of the
terms shown in the figure.
Rev. PrB | Page 13 of 16
50%
50%
V
N
± V
OS
50%
DIFFERENTIAL
INPUT VOLTAGE
LATCH ENABLE
Q OUTPUT
Q OUTPUT
LATCH ENABLE
t
H
t
PDL
t
PDH
t
PLOH
t
PLOL
t
R
t
F
V
IN
V
OD
t
S
t
PL
0
Figure 25. System Timing Diagram
Table 4. Timing Descriptions
Symbol
Timing
t
PDH
Input to output high delay
Description
Propagation delay measured from the time the input signal crosses the reference (± the
input offset voltage) to the 50% point of an output low-to-high transition.
Propagation delay measured from the time the input signal crosses the reference (± the
input offset voltage) to the 50% point of an output high-to-low transition.
Propagation delay measured from the 50% point of the latch enable signal low-to-high
transition to the 50% point of an output low-to-high transition.
Propagation delay measured from the 50% point of the latch enable signal low-to-high
transition to the 50% point of an output high-to-low transition.
Minimum time after the negative transition of the latch enable signal that the input signal
must remain unchanged to be acquired and held at the outputs.
Minimum time that the latch enable signal must be high to acquire an input signal change.
Minimum time before the negative transition of the latch enable signal that an input
signal change must be present to be acquired and held at the outputs.
Amount of time required to transition from a low to a high output as measured at the
20% and 80% points.
Amount of time required to transition from a high to a low output as measured at the
20% and 80% points.
Difference between the input voltages V
A
and V
B
.
t
PDL
Input to output low delay
t
PLOH
Latch enable to output high delay
t
PLOL
Latch enable to output low delay
t
H
Minimum hold time
t
PL
t
S
Minimum latch enable pulse width
Minimum setup time
t
R
Output rise time
t
F
Output fall time
V
OD
Voltage overdrive
相關PDF資料 |
PDF描述 |
|---|---|
| ADCMP572BCP | Ultrafast 3.3 V Single-Supply Comparators |
| ADCMP573 | Ultrafast 3.3 V Single-Supply Comparators |
| ADCMP573BCP | Ultrafast 3.3 V Single-Supply Comparators |
| ADCMP580 | Ultrafast SiGe Voltage Comparators |
| ADCMP580_05 | Ultrafast SiGe Voltage Comparators |
相關代理商/技術參數 |
參數描述 |
|---|---|
| ADCMP572_05 | 制造商:AD 制造商全稱:Analog Devices 功能描述:Ultrafast 3.3 V/5 V Single-Supply SiGe Comparators |
| ADCMP572BCP | 制造商:AD 制造商全稱:Analog Devices 功能描述:Ultrafast 3.3 V Single-Supply Comparators |
| ADCMP572BCP-R2 | 制造商:Analog Devices 功能描述:Comparator Single 5.4V 16-Pin LFCSP EP T/R 制造商:Rochester Electronics LLC 功能描述:SINGLE SUPPLY, CML ON XFCB3.0- - Bulk |
| ADCMP572BCP-RL7 | 制造商:Analog Devices 功能描述:Comparator Single 5.4V 16-Pin LFCSP EP T/R |
| ADCMP572BCP-WP | 制造商:Analog Devices 功能描述:Comparator Single 5.4V 16-Pin LFCSP EP |
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