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參數(shù)資料
| 型號： | ADCMP573 |
| 廠商： | Analog Devices, Inc. |
| 英文描述： | Ultrafast 3.3 V Single-Supply Comparators |
| 中文描述： | 超快3.3 V單電源比較 |
| 文件頁數(shù)： | 6/16頁 |
| 文件大小： | 412K |
| 代理商： | ADCMP573 |
ADCMP572/ADCMP573
Preliminary Technical Data
PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
Rev. PrB | Page 6 of 16
0
5
V
C
6
L
7
L
8
V
C
/
T
ADCMP572
ADCMP573
TOP VIEW
(Not to Scale)
1
V
TP
PIN1
2
V
P
3
V
N
4
V
TN
16
V
C
15
G
14
H
13
G
V
CCO
12
Q
11
Q
10
V
CCO
9
Figure 2. ADCMP572/ADCMP573 Pin Configuration
Table 3. Pin Function Descriptions
Pin No.
Mnemonic
1
V
TP
2
V
P
3
V
N
4
V
TN
5, 16
V
CCI
6
LE
Description
Termination Resistor Return Pin for V
P
Input.
Noninverting Analog Input.
Inverting Analog Input.
Termination Resistor Return Pin for V
N
Input.
Positive Supply Voltage for Input Stage.
Latch Enable Input Pin, Inverting Side.
In compare mode (LE = low), the output tracks changes at the input of the comparator.
In latch mode (LE = high), the output reflects the input state just prior to the comparator’s being
placed in latch mode. LE must be driven in compliment with LE.
Latch Enable Input Pin, Noninverting Side.
In compare mode (LE = high), the output tracks changes at the input of the comparator.
In latch mode (LE = low), the output reflects the input state just prior to the comparator’s being
placed in latch mode. LE must be driven in compliment with LE.
Termination Return Pin for the LE/LE Input Pins.
For the ADCMP572 (CML output stage), this pin should be connected to the positive V
CCO
supply.
For the ADCMP573 (RSPECL output stage), this pin should be connected to the V
CCO
– 2 V
termination potential.
Ground.
Positive Supply Voltage for the CML/RSPECL Output Stage.
Inverting Output. Q is at logic low if the analog voltage at the noninverting input, V
P
, is greater than
the analog voltage at the inverting input, V
N
, provided the comparator is in compare mode. See the
LE/LE description (Pins 6 and 7) for more information.
Noninverting Output. Q is at logic high if the analog voltage at the noninverting input V
P
is greater
than the analog voltage at the inverting input, V
N
, provided the comparator is in compare mode. See
the LE/LE description (Pins 6 and 7) for more information.
Hysteresis Control Pin. Leave this pin disconnected for zero hysteresis. Connect to GND with a
suitably sized resistor to add the desired amount of hysteresis. Refer to Figure 7 for proper sizing of
R
HYS
hysteresis control resistor.
The metallic back surface of the package is not electrically connected to any part of the circuit, and it
can be left floating for best electrical isolation between the package handle and the substrate of the
die. But it can also be soldered to the application board if improved thermal and/or mechanical
stability is desired.
7
LE
8
V
CCO
/V
TT
13, 15
9, 12
10
GND
V
CCO
Q
11
Q
14
HYS
Heatsink
N/C
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