欧美成人免费电影,国产欧美一区二区三区精品酒店,精品国产a毛片,色网在线免费观看

參數資料
型號: ADCMP606BKSZ-RL
廠商: ANALOG DEVICES INC
元件分類: 運動控制電子
英文描述: Rail-to-Rail, Very Fast, 2.5 V to 5.5 V, Single-Supply CML Comparators
中文描述: COMPARATOR, 5000 uV OFFSET-MAX, 2.1 ns RESPONSE TIME, PDSO6
封裝: ROHS COMPLIANT, MO-203AB, SC-70, 6 PIN
文件頁數: 5/16頁
文件大?。?/td> 280K
代理商: ADCMP606BKSZ-RL
ADCMP606/ADCMP607
TIMING INFORMATION
Figure 2 illustrates the ADCMP606/ADCMP607 latch timing relationships. Table 2 provides definitions of the terms shown in Figure 2.
Rev. 0 | Page 5 of 16
1.1V
50%
V
N
± V
OS
DIFFERENTIAL
INPUT VOLTAGE
LATCH ENABLE
Q OUTPUT
t
H
t
PDL
t
PLOH
t
F
V
IN
V
OD
t
S
t
PL
50%
Q OUTPUT
t
PDH
t
PLOL
t
R
0
Figure 2. System Timing Diagram
Table 2. Timing Descriptions
Symbol
Timing
t
F
Output fall time
Description
Amount of time required to transition from a high to a low output as measured at the 20%
and 80% points.
Minimum time after the negative transition of the latch enable signal that the input signal
must remain unchanged to be acquired and held at the outputs.
Propagation delay measured from the time the input signal crosses the reference (± the
input offset voltage) to the 50% point of an output low-to-high transition.
Propagation delay measured from the time the input signal crosses the reference (± the
input offset voltage) to the 50% point of an output high-to-low transition.
Minimum time that the latch enable signal must be high to acquire an input signal change.
Propagation delay measured from the 50% point of the latch enable signal low-to-high
transition to the 50% point of an output low-to-high transition.
Propagation delay measured from the 50% point of the latch enable signal low-to-high
transition to the 50% point of an output high-to-low transition.
Amount of time required to transition from a low to a high output as measured at the 20%
and 80% points.
Minimum time before the negative transition of the latch enable signal occurs that an
input signal change must be present to be acquired and held at the outputs.
Difference between the input voltages V
A
and V
B
.
t
H
Minimum hold time
t
PDH
Input to output high delay
t
PDL
Input to output low delay
t
PL
t
PLOH
Minimum latch enable pulse width
Latch enable to output high delay
t
PLOL
Latch enable to output low delay
t
R
Output rise time
t
S
Minimum setup time
V
OD
Voltage overdrive
相關PDF資料
PDF描述
ADCMP607 Rail-to-Rail, Very Fast, 2.5 V to 5.5 V, Single-Supply CML Comparators
ADCMP607BCPZ-R2 Rail-to-Rail, Very Fast, 2.5 V to 5.5 V, Single-Supply CML Comparators
ADCMP607BCPZ-R7 Rail-to-Rail, Very Fast, 2.5 V to 5.5 V, Single-Supply CML Comparators
ADCMP607BCPZ-WP Rail-to-Rail, Very Fast, 2.5 V to 5.5 V, Single-Supply CML Comparators
ADCMP609 Rail-to-Rail, Fast, Low Power 2.5 V to 5.5 V, Single-Supply TTL/CMOS Comparator
相關代理商/技術參數
參數描述
ADCMP607 制造商:AD 制造商全稱:Analog Devices 功能描述:Rail-to-Rail, Very Fast, 2.5 V to 5.5 V, Single-Supply CML Comparators
ADCMP607BCPZ-R2 功能描述:IC COMP TTL/CMOS 1CHAN 12-LFCSP RoHS:是 類別:集成電路 (IC) >> 線性 - 比較器 系列:- 產品培訓模塊:Lead (SnPb) Finish for COTS Obsolescence Mitigation Program 標準包裝:2,500 系列:- 類型:通用 元件數:1 輸出類型:CMOS,推挽式,滿擺幅,TTL 電壓 - 電源,單路/雙路(±):2.5 V ~ 5.5 V,±1.25 V ~ 2.75 V 電壓 - 輸入偏移(最小值):5mV @ 5.5V 電流 - 輸入偏壓(最小值):1pA @ 5.5V 電流 - 輸出(標準):- 電流 - 靜態(最大值):24µA CMRR, PSRR(標準):80dB CMRR,80dB PSRR 傳輸延遲(最大):450ns 磁滯:±3mV 工作溫度:-40°C ~ 85°C 封裝/外殼:6-WFBGA,CSPBGA 安裝類型:表面貼裝 包裝:管件 其它名稱:Q3554586
ADCMP607BCPZ-R7 功能描述:IC COMP TTL/CMOS 1CHAN 12-LFCSP RoHS:是 類別:集成電路 (IC) >> 線性 - 比較器 系列:- 產品培訓模塊:Lead (SnPb) Finish for COTS Obsolescence Mitigation Program 標準包裝:2,500 系列:- 類型:通用 元件數:1 輸出類型:CMOS,推挽式,滿擺幅,TTL 電壓 - 電源,單路/雙路(±):2.5 V ~ 5.5 V,±1.25 V ~ 2.75 V 電壓 - 輸入偏移(最小值):5mV @ 5.5V 電流 - 輸入偏壓(最小值):1pA @ 5.5V 電流 - 輸出(標準):- 電流 - 靜態(最大值):24µA CMRR, PSRR(標準):80dB CMRR,80dB PSRR 傳輸延遲(最大):450ns 磁滯:±3mV 工作溫度:-40°C ~ 85°C 封裝/外殼:6-WFBGA,CSPBGA 安裝類型:表面貼裝 包裝:管件 其它名稱:Q3554586
ADCMP607BCPZ-WP 功能描述:IC COMP TTL/CMOS 1CHAN 12-LFCSP RoHS:是 類別:集成電路 (IC) >> 線性 - 比較器 系列:- 產品培訓模塊:Lead (SnPb) Finish for COTS Obsolescence Mitigation Program 標準包裝:50 系列:- 類型:帶電壓基準 元件數:4 輸出類型:開路漏極 電壓 - 電源,單路/雙路(±):2.5 V ~ 11 V,±1.25 V ~ 5.5 V 電壓 - 輸入偏移(最小值):10mV @ 5V 電流 - 輸入偏壓(最小值):- 電流 - 輸出(標準):0.015mA @ 5V 電流 - 靜態(最大值):8.5µA CMRR, PSRR(標準):80dB CMRR,80dB PSRR 傳輸延遲(最大):- 磁滯:- 工作溫度:0°C ~ 70°C 封裝/外殼:16-SOIC(0.154",3.90mm 寬) 安裝類型:表面貼裝 包裝:管件 產品目錄頁面:1386 (CN2011-ZH PDF)
ADCMP608 制造商:AD 制造商全稱:Analog Devices 功能描述:Rail-to-Rail, Fast, Low Power 2.5 V to 5.5 V, Single-Supply TTL/CMOS Comparator
主站蜘蛛池模板: 安化县| 张家界市| 佛教| 灵石县| 巴林右旗| 漠河县| 信丰县| 扶绥县| 张家界市| 黑龙江省| 衡阳市| 黔江区| 宜章县| 蚌埠市| 榆林市| 阜城县| 乌兰浩特市| 宜宾市| 工布江达县| 温州市| 庆元县| 尼木县| 竹山县| 威远县| 建湖县| 岳池县| 嘉禾县| 海伦市| 襄樊市| 泽州县| 明水县| 蒲城县| 云霄县| 呈贡县| 高青县| 涡阳县| 白山市| 镶黄旗| 曲阳县| 清河县| 霍林郭勒市|