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參數(shù)資料
型號(hào)： ADE7169ACPF16
廠商： ANALOG DEVICES INC
元件分類： 模擬信號(hào)調(diào)理
英文描述： Single-Phase Energy Measurement IC with 8052 MCU, RTC and LCD driver
中文描述： ANALOG CIRCUIT, QCC64
封裝： 9 X 9MM, MO-220VMMD, LFCSP-64
文件頁數(shù)： 11/140頁
文件大小： 1359K
代理商： ADE7169ACPF16
Preliminary Technical Data
ADE7169F16
TIMING SPECIFICATIONS
AC inputs during testing are driven at V
SWOUT
– 0.5 V for Logic 1 and 0.45 V for Logic 0. Timing measurements are made at V
IH
min for
Logic 1 and V
IL
max for Logic 0 as shown in Figure 2.
Rev. PrD | Page 11 of 140
For timing purposes, a port pin is no longer floating when a 100 mV change from load voltage occurs. A port pin begins to float when a
100 mV change from the loaded V
OH
/V
OL
level occurs as shown in Figure 2.
C
LOAD
for all outputs = 80 pF, unless otherwise noted.
V
DD
= 2.7 V to 3.6 V; all specifications T
MIN
to T
MAX
, unless otherwise noted.
Table 2. CLOCK INPUT (External Clock Driven XTAL1) Parameter
t
CK
XTAL1 Period
t
CKL
XTAL1 Width Low
t
CKH
XTAL1 Width High
t
CKR
XTAL1 Rise Time
t
CKF
XTAL1 Fall Time
1/t
CORE
Core Clock Frequency
1
32.768 kHz External Crystal
Typ
30.52
6.26
6.26
9
9
TBD
Unit
μs
μs
μs
ns
ns
MHz
Min
TBD
Max
4.096
1
ADE7129F16 internal PLL locks onto a multiple (512 times) of the 32.768 kHz external crystal frequency to provide a stable 12.58 MHz internal clock for the system. The
core can operate at this frequency or at a binary submultiple called Core_Clk, selected via the PLLCON SFR.
DV
DD
– 0.5V
0.45V
0.2DV
+ 0.9V
TEST POINTS
0.2DV
DD
– 0.1V
V
LOAD
– 0.1V
V
LOAD
V
LOAD
+ 0.1V
TIMING
REFERENCE
POINTS
V
LOAD
– 0.1V
V
LOAD
V
LOAD
– 0.1V
0
Figure 2. Timing Waveform Characteristics
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