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參數資料
| 型號： | ADE7753 |
| 廠商： | Analog Devices, Inc. |
| 英文描述： | Active and Apparent Energy Metering IC with di/dt sensor interface |
| 中文描述： | 主動與迪視電能計量IC / dt的傳感器接口 |
| 文件頁數： | 4/38頁 |
| 文件大小： | 449K |
| 代理商： | ADE7753 |
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ADE7753
ADE7753 TIMNG CHARACTERISTICS
1,2
–4–
REV. PrF 10/02
PRELIMINARY TECHNICAL DATA
CS
SCLK
DIN
A4
A3 A2
A1 A0
DB7
Most Significant Byte
t
1
t
2
t
3
t
4
t
5
t
8
1
DB0
DB7
DB0
t
6
Least Significant Byte
t
7
t
7
0
0
Command Byte
CS
SCLK
DIN
A4 A3 A2
A1 A0
t
1
t
11
t
11
t
9
DB7
DOUT
t
12
DB0
DB0
DB7
t
10
t
13
Most Significant Byte
Least Significant Byte
0
0
0
Command Byte
Serial Write T iming
Serial Read T iming
Parameter
A,B Versions
Units
Test Conditions/Comments
Write timing
t
1
t
2
t
3
t
4
t
5
t
6
t
7
t
8
Read timing
t
9
20
150
150
10
5
T BD
T BD
100
ns (min)
ns (min)
ns (min)
ns (min)
ns (min)
ns (min)
ns (min)
ns (min)
CS
falling edge to first SCLK falling edge
SCLK logic high pulse width
SCLK logic low pulse width
Valid Data Set up time before falling edge of SCLK
Data Hold time after SCLK falling edge
Minimum time between the end of data byte transfers.
Minimum time between byte transfers during a serial write.
CS
Hold time after SCLK falling edge.
3.1
us (min)
Minimum time between read command (i.e. a write to Communication
Reigster) and data read.
Minimum time between data byte transfers during a multibyte read.
Data access time after SCLK rising edge following a write to the
C ommunications Register
Bus relinquish time after falling edge of SCLK .
t
10
t
113
T BD
30
ns (min)
ns (min)
t
124
100
10
100
10
ns (max)
ns (min)
ns (max)
ns (min)
t
134
Bus relinquish time after rising edge of
CS
.
NOT ES
1
Sample tested during initial release and after any redesign or process change that may affect this parameter. All input signals are specified with tr = tf = 5ns (10% to 90%)
and timed from a voltage level of 1.6V.
2
See timing diagram below and Serial Interface section of this data sheet.
3
Measured with the load circuit in Figure 1 and defined as the time required for the output to cross 0.8V or 2.4V.
4
Derived from the measured time taken by the data outputs to change 0.5V when loaded with the circuit in Figure 1. T he measured number is then extrapolated back to
remove the effects of charging or discharging the 50pF capacitor. T his means that the time quoted in the timing characteristics is the true bus relinquish time of the part
and is independent of the bus loading.
(AV
DD
= DV
DD
= 5V ± 5%, AGND = DGND = 0V, On-Chip Reference,
CLKIN= 3.579545MHz XTAL, TMNto TMAX = -40°C to +85°C)
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| ADE7753ARS | Active and Apparent Energy Metering IC with di/dt sensor interface |
| ADE7753ARSRL | Active and Apparent Energy Metering IC with di/dt sensor interface |
| ADE7754 | ADE7754 |
| ADE7754AR | ADE7754 |
| ADE7754ARRL | ADE7754 |
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| ADE7753ARSZ | 功能描述:IC ENERGY METERING 1PHASE 20SSOP RoHS:是 類別:集成電路 (IC) >> PMIC - 能量測量 系列:- 產品培訓模塊:Lead (SnPb) Finish for COTS Obsolescence Mitigation Program 標準包裝:2,500 系列:* |
| ADE7753ARSZ | 制造商:Analog Devices 功能描述:ENERGY METERING IC |
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