- 您現在的位置：買賣IC網 > PDF目錄373980 > ADE7756 (Analog Devices, Inc.) Active Energy Metering IC with Serial Interface PDF資料下載
參數資料
| 型號： | ADE7756 |
| 廠商： | Analog Devices, Inc. |
| 英文描述： | Active Energy Metering IC with Serial Interface |
| 中文描述： | 有源電能計量IC串行接口 |
| 文件頁數： | 8/15頁 |
| 文件大小： | 3563K |
| 代理商： | ADE7756 |
EVAL-ADE7756EB
–8–
REV. PrB 01/01
PRELIMINARY TECHNICAL DATA
Measuring CT Phase Errors using the ADE7756
The ADE7756 itself can be used to measure a CT (and
external components) phase error during calibration. The
assumption is that the ADE7756 has no internal phase
error (PHCAL = 00 hex) and the error due to external
components is small (<0.5°). The procedure is based on a
two point measurement, at PF=1 and PF = 0.5 (lag). The
PF is set up using the test bench source and this source
must be very accurate. The ADE7756 should be config-
ured for energy measurement mode.
An energy measurement is first made with PF=1 (mea-
surement A). A second energy measurement should be
made at PF=0.5 (measurement B). The frequency output
CF can be used for this measurement. Using the formula
shown below the phase error is easily calculated:
=
°
3
2
2
tan
)
(
1
A
A
B
Error
Phase
For example, using the frequency output CF to measure
power, a frequency of 3.66621Hz is recorded for a PF=1.
The PF is then set to 0.5 lag and a measurement of
1.83817Hz is obtained. Using the formula above the
phase error on Channel 1 is calculated as:
°
+
=
=
°
091
.
3
2
66621
.
2
66621
.
83817
.
tan
)
(
1
Error
Phase
The formula will also give the correct sign for the phase
error. In this example the phase error is calculated as
+0.091° at the input to the Channel 1 of ADE7756. This
means that the CT has introduced a phase lead of 0.091°.
Therefore the phase difference at thr input to Channel 1 is
now 59.89° lag instead of 60° lag. Determining whether
the error is a lead or lag can also be figured intuitively
from the frequency output. Figure 11 shows how the
output frequency varies with phase (cos{
φ
}). Since the
output frequency B (1.83817Hz) at the PF=0.5 lag setting
in the example is actually greater than A/2 (1.833105Hz),
this means the phase error between Channel 1 and Chan-
nel 2 was actually less than 60°. This means there was
additional lead in Channel 1 due to the CT.
60
PF=1
PF=0.5
PF<0.5
PF>0.5
CF (Hz)
PF=0
Phase lag
360
Frequency B > A/2
Phase difference < 60
lag
Figure 10
—
CF Frequency Vs Phase(PF)
Using the Phase Calibration to correct
small (<0.5°) external phase errors
From the previous example it is seen that the CT intro-
duced a phase lead in Channel 1 of 0.091° . Therefore
instead of 60° phase difference between Channel 1 and
Channel 2, it is actually 59.89°. In order to bring the
phase difference back to 60°, the phase compensation
circuit in Channel 2 is used to introduce an extra lead of
0.091°. This is achieved by reducing the amount of time
delay in Channel 2.
The maximum time delay adjustment in Channel 2 is
±143μs with a CLKIN of 3.579545MHz. The PHCAL
register is a signed 2's complement 6 bit register. There-
fore each LSB is equivalent to 4.47μs. In this example the
line frequency is 50Hz. This means each LSB is equiva-
lent to (360° x 4.47μs x 50) = 0.08°. To introduce a lead
of 0.091° the delay in Channel 2 must be reduced. This is
achieved by writing -1 (FFh) or +0.08° to the PHCAL
register.
Figure 11
—
Writing to the PHCAL register to correct
phase error
Correcting large external phase errors
In this example the phase correction range at 50Hz is only
approximatey ±2.5°. However it is best to only use the
PHCAL register for small phase corrections, i.e., <0.5°.
If larger corrections are required the larger part of the
correction can be made using external passive component.
For example the resistors in the anti-alias filter can be
modified to shift the corner frequency of the filter so as to
introduce more or less lag. The lag through the anti-alias
filters with 1k
and 33nF is 0.56° at 50Hz. Fine adjust
can be made with the PHCAL register. Note that typically
CT phase shift will not vary significantly from part to
part. If a CT phase shift is 1°, then the part to part
variation should only be about ±0.1°. Therefore the bulk
of the phase shift (1°) can be canceled with fixed compo-
nent values at design. The remaining small adjustments
can be made in production using the PHCAL register.
相關PDF資料 |
PDF描述 |
|---|---|
| ADE7756AN | Active Energy Metering IC with Serial Interface |
| ADE7756AN-REF | Active Energy Metering IC with Serial Interface |
| ADE7756ARS | Active Energy Metering IC with Serial Interface |
| ADE7756ARSRL | Active Energy Metering IC with Serial Interface |
| ADE7756BN | Active Energy Metering IC with Serial Interface |
相關代理商/技術參數 |
參數描述 |
|---|---|
| ADE7756AN | 制造商:Analog Devices 功能描述:Energy Measurement 20-Pin PDIP |
| ADE7756AN-REF | 制造商:AD 制造商全稱:Analog Devices 功能描述:Active Energy Metering IC with Serial Interface |
| ADE7756ARS | 制造商:Analog Devices 功能描述:Energy Measurement 20-Pin SSOP 制造商:Analog Devices 功能描述:ENERGY METERING IC WITH SERIAL INTERFACE - Rail/Tube 制造商:Rochester Electronics LLC 功能描述:ENERGY METERING IC WITH SERIAL INTERFACE - Bulk |
| ADE7756ARSRL | 制造商:Analog Devices 功能描述:Energy Measurement 20-Pin SSOP T/R 制造商:Analog Devices 功能描述:ENERGY METERING IC WITH SERIAL INTERFACE - Tape and Reel |
| ADE7756ARSZ | 制造商:Analog Devices 功能描述:Energy Measurement 20-Pin SSOP 制造商:Analog Devices 功能描述:PBFR ENERGYMETERICW/ SERIAL INTERFACE - Rail/Tube |
發布緊急采購，3分鐘左右您將得到回復。