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參數(shù)資料
| 型號： | ADE7768 |
| 廠商： | Analog Devices, Inc. |
| 英文描述： | Energy Metering IC with Integrated Oscillator and Positive Power Accumulation |
| 中文描述： | 電能計量IC整合的振蕩器和積累的積極力量 |
| 文件頁數(shù)： | 4/20頁 |
| 文件大小： | 299K |
| 代理商： | ADE7768 |
ADE7768
Parameter
POWER SUPPLY
V
DD
I
DD
Rev. A | Page 4 of 20
Value
4.75
5.25
5
Unit
V min
V max
mA max
Test Conditions/Comments
For specified performance
5 V – 5%
5 V + 5%
Typically 4 mA
1
See the Terminology section for an explanation of specifications.
2
See the figures in the Typical Performance Characteristics section.
3
Sample tested during initial release and after any redesign or process change that may affect this parameter.
TIMING CHARACTERISTICS
V
DD
= 5 V ± 5%, AGND = DGND = 0 V, on-chip reference, RCLKIN = 6.2 kΩ, 0.5% ± 50 ppm/°C, T
MIN
to T
MAX
= –40°C to +85°C,
unless otherwise noted. Sample tested during initial release and after any redesign or process change that may affect this parameter.
See Figure 2.
Table 2.
Parameter
Specifications
Unit
Test Conditions/Comments
t
11
t
2
t
3
t
41, 2
t
5
t
6
120
See Table 6
1/2 t
2
90
See Table 7
2
ms
sec
sec
ms
sec
μs
F1 and F2 pulse width (logic low)
Output pulse period. See the Transfer Function section.
Time between the F1 and F2 falling edges.
CF pulse width (logic high).
CF pulse period. See the Transfer Function section.
Minimum time between the F1 and F2 pulses.
1
The pulse widths of F1, F2, and CF are not fixed for higher output frequencies. See the Frequency Outputs section.
2
The CF pulse is always 35 μs in high frequency mode. See the Frequency Outputs section and Table 7.
F1
F2
CF
t
1
t
5
t
4
t
2
t
6
t
3
0
Figure 2. Timing Diagram for Frequency Outputs
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