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參數資料
| 型號： | ADF4107 |
| 廠商： | Analog Devices, Inc. |
| 英文描述： | PLL Frequency Synthesizer |
| 中文描述： | 鎖相環頻率合成器 |
| 文件頁數： | 18/20頁 |
| 文件大小： | 792K |
| 代理商： | ADF4107 |
ADF4107
APPLICATIONS
Local Oscillator for LMDS Base Station
Transmitter
Rev. 0 | Page 18 of 20
Figure 27 below shows the ADF4107 being used with a VCO to
produce the LO for an LMDS base station.
The reference input signal is applied to the circuit at FREF
IN
and, in this case, is terminated in 50 . A typical base station
system would have either a TCXO or an OCXO driving the
reference input without any 50 termination.
To have a channel spacing of 1 MHz at the output, the 10 MHz
reference input must be divided by 10, using the on-chip
reference divider of the ADF4107.
The charge pump output of the ADF4107 (Pin 2) drives the
loop filter. In calculating the loop filter component values, a
number of items need to be considered. In this example, the
loop filter was designed so that the overall phase margin for the
system would be 45°.
Other PLL system specifications are:
K
D
= 5.0 mA
K
V
= 80 MHz/V
Loop Bandwidth = 70 kHz
F
PFD
= 1 MHz
N = 6300
Extra Reference Spur Attenuation = 10 dB
All of these specifications are needed and used to derive the
loop filter component values shown in Figure 27.
Figure 27 gives a typical phase noise performance of
83 dBc/Hz at 1 kHz offset from the carrier. Spurs are better
than 70 dBc.
The loop filter output drives the VCO, which, in turn, is fed
back to the RF input of the PLL synthesizer and also drives the
RF output terminal. A T-circuit configuration provides 50
matching between the VCO output, the RF output, and the RF
IN
terminal of the synthesizer.
In a PLL system, it is important to know when the system is in
lock. In Figure 27, this is accomplished by using the MUXOUT
signal from the synthesizer. The MUXOUT pin can be
programmed to monitor various internal signals in the
synthesizer. One of these is the LD or lock detect signal.
ADF4107
CE
CLK
DATA
LE
1000pF
1000pF
REFIN
100pF
CP
MUXOUT
C
A
D
100pF
820pF
47pF
100pF
51
1.7k
7.5k
100pF
18
NOTE
DECOUPLING CAPACITORS (0.1
μ
F/10pF) ON AV
, DV
,
V
OF THE ADF4107 AND ON V
OF THE V956ME01 HAVE
BEEN OMITTED FROM THE DIAGRAM TO AID CLARITY.
S
R
SET
RF
IN
A
RF
IN
B
AV
DD
DV
DD
V
P
FREF
IN
V
DD
V
P
LOCK
DETECT
V
CC
V956ME01
1, 3, 4, 5, 7, 8,
9, 11, 12, 13
18
18
100pF
RF
OUT
5.1k
7
15
16
8
2
14
6
5
1
9
4
3
14
2
10
51
Figure 27. 6.3 GHz Local Oscillator Using the ADF4107
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PDF描述 |
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| ADF4107BCP | 16-9 (4 Contacts) Pin Insert; For Use With:Amphenol MIL-C-5015 97 Series Circular Connectors; No. of Contacts:4 |
| ADF4107BCP-REEL | PLL Frequency Synthesizer |
| ADF4107BCP-REEL7 | PLL Frequency Synthesizer |
| ADF4107BRU | Circular Connector; No. of Contacts:128; Series:LJT02R; Body Material:Aluminum; Connecting Termination:Crimp; Connector Shell Size:25; Circular Contact Gender:Socket; Circular Shell Style:Box Mount Receptacle |
| ADF4107BRU-REEL | Circular Connector; No. of Contacts:61; Series:LJT02R; Body Material:Aluminum; Connecting Termination:Crimp; Connector Shell Size:25; Circular Contact Gender:Pin; Circular Shell Style:Box Mount Receptacle; Insert Arrangement:25-61 |
相關代理商/技術參數 |
參數描述 |
|---|---|
| ADF4107BCP | 制造商:Analog Devices 功能描述:PLL Frequency Synthesizer Single 20-Pin LFCSP EP |
| ADF4107BCP-REEL | 制造商:Analog Devices 功能描述:PLL Frequency Synthesizer Single 20-Pin LFCSP EP T/R |
| ADF4107BCP-REEL7 | 制造商:Analog Devices 功能描述:PLL Frequency Synthesizer Single 20-Pin LFCSP EP T/R |
| ADF4107BCPZ | 功能描述:IC PLL FREQ SYNTHESIZER 20LFCSP RoHS:是 類別:集成電路 (IC) >> 時鐘/計時 - 時鐘發生器，PLL，頻率合成器 系列:- 標準包裝:1,000 系列:Precision Edge® 類型:時鐘/頻率合成器 PLL:無 輸入:CML，PECL 輸出:CML 電路數:1 比率 - 輸入:輸出:2:1 差分 - 輸入:輸出:是/是 頻率 - 最大:10.7GHz 除法器/乘法器:無/無 電源電壓:2.375 V ~ 3.6 V 工作溫度:-40°C ~ 85°C 安裝類型:表面貼裝 封裝/外殼:16-VFQFN 裸露焊盤，16-MLF? 供應商設備封裝:16-MLF?（3x3） 包裝:帶卷 (TR) 其它名稱:SY58052UMGTRSY58052UMGTR-ND |
| ADF4107BCPZ | 制造商:Analog Devices 功能描述:PLL, FREQUENCY SYNTHESIZER, 7GHZ, LFCSP- |
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