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參數資料
| 型號： | ADF4117 |
| 廠商： | Analog Devices, Inc. |
| 英文描述： | RF PLL Frequency Synthesizers |
| 中文描述： | 射頻鎖相環頻率合成器 |
| 文件頁數： | 17/20頁 |
| 文件大小： | 226K |
| 代理商： | ADF4117 |
ADF4116/ADF4117/ADF4118
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17
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REV. 0
The Initialization Latch
When C2, C1 = 1, 1 then the Initialization Latch is programmed.
This is essentially the same as the Function Latch (programmed
when C2, C1 = 1, 0).
However, when the Initialization Latch is programmed there is a
additional internal reset pulse applied to the R and N counters.
This pulse ensures that the N counter is at load point when the
N counter data is latched and the device will begin counting in
close phase alignment.
If the Latch is programmed for synchronous power-down (CE
pin is High; PD1 bit is High; PD2 bit is Low), the internal pulse
also triggers this power-down. The prescaler reference and the
oscillator input buffer are unaffected by the internal reset pulse and
so close phase alignment is maintained when counting resumes.
When the first N counter data is latched after initialization, the
internal reset pulse is again activated. However, successive N
counter loads after this will not trigger the internal reset pulse.
Device Programming After Initial Power-Up
After initially powering up the device, there are three ways to
program the device.
Initialization Latch Method
Apply V
DD
.
Program the Initialization Latch (“11” in 2 LSBs of input word).
Make sure that F1 bit is programmed to “0.” Then do an R load
(“00” in 2 LSBs). Then do an N load (“01” in 2 LSBs). When the
Initialization Latch is loaded, the following occurs:
1. The function latch contents are loaded.
2. An internal pulse resets the R, N and timeout counters to
load state conditions and also three-states the charge pump.
Note that the prescaler bandgap reference and the oscillator
input buffer are unaffected by the internal reset pulse,
allowing close phase alignment when counting resumes.
3. Latching the first N counter data after the initialization word
will activate the same internal reset pulse. Successive N loads
will not trigger the internal reset pulse unless there is another
initialization.
The CE Pin Method
Apply V
DD
.
Bring CE low to put the device into power-down. This is an
asynchronous power-down in that it happens immediately.
Program the Function Latch (10). Program the R Counter
Latch (00). Program the N Counter Latch (01). Bring CE high
to take the device out of power-down. The R and N counter will
now resume counting in close alignment.
Note that after CE goes high, a duration of 1
μ
s may be required
for the prescaler bandgap voltage and oscillator input buffer bias
to reach steady state.
CE can be used to power the device up and down in order to
check for channel activity. The input register does not need to
be reprogrammed each time the device is disabled and enabled
as long as it has been programmed at least once after V
CC
was
initially applied.
The Counter Reset Method
Apply V
DD
.
Do a Function Latch Load (“10” in 2 LSBs). As part of this,
load “1” to the F1 bit. This enables the counter reset. Do an R
Counter Load (“00” in 2 LSBs). Do an N Counter Load (“01”
in 2 LSBs). Do a Function Latch Load (“10” in 2 LSBs). As
part of this, load “0” to the F1 bit. This disables the counter reset.
This sequence provides the same close alignment as the initial-
ization method. It offers direct control over the internal reset.
Note that counter reset holds the counters at load point and
three-states the charge pump, but does not trigger synchronous
power-down. The counter reset method requires an extra func-
tion latch load compared to the initialization latch method.
相關PDF資料 |
PDF描述 |
|---|---|
| ADF4153 | Fractional-N Frequency Synthesizer |
| ADF4153BCP | Fractional-N Frequency Synthesizer |
| ADF4153BCP-REEL | Fractional-N Frequency Synthesizer |
| ADF4153BCP-REEL7 | Fractional-N Frequency Synthesizer |
| ADF4153BRU | Fractional-N Frequency Synthesizer |
相關代理商/技術參數 |
參數描述 |
|---|---|
| ADF4117BCP | 制造商:AD 制造商全稱:Analog Devices 功能描述:RF PLL Frequency Synthesizers |
| ADF4117BRU | 功能描述:IC PLL FREQ SYNTHESIZER 16-TSSOP RoHS:否 類別:集成電路 (IC) >> 時鐘/計時 - 時鐘發生器，PLL，頻率合成器 系列:- 標準包裝:1,000 系列:Precision Edge® 類型:時鐘/頻率合成器 PLL:無 輸入:CML，PECL 輸出:CML 電路數:1 比率 - 輸入:輸出:2:1 差分 - 輸入:輸出:是/是 頻率 - 最大:10.7GHz 除法器/乘法器:無/無 電源電壓:2.375 V ~ 3.6 V 工作溫度:-40°C ~ 85°C 安裝類型:表面貼裝 封裝/外殼:16-VFQFN 裸露焊盤，16-MLF? 供應商設備封裝:16-MLF?（3x3） 包裝:帶卷 (TR) 其它名稱:SY58052UMGTRSY58052UMGTR-ND |
| ADF4117BRU-REEL | 制造商:Analog Devices 功能描述:PLL Frequency Synthesizer Single 16-Pin TSSOP T/R |
| ADF4117BRU-REEL7 | 功能描述:IC PLL FREQ SYNTHESIZER 16-TSSOP RoHS:否 類別:集成電路 (IC) >> 時鐘/計時 - 時鐘發生器，PLL，頻率合成器 系列:- 標準包裝:1,000 系列:Precision Edge® 類型:時鐘/頻率合成器 PLL:無 輸入:CML，PECL 輸出:CML 電路數:1 比率 - 輸入:輸出:2:1 差分 - 輸入:輸出:是/是 頻率 - 最大:10.7GHz 除法器/乘法器:無/無 電源電壓:2.375 V ~ 3.6 V 工作溫度:-40°C ~ 85°C 安裝類型:表面貼裝 封裝/外殼:16-VFQFN 裸露焊盤，16-MLF? 供應商設備封裝:16-MLF?（3x3） 包裝:帶卷 (TR) 其它名稱:SY58052UMGTRSY58052UMGTR-ND |
| ADF4117BRUZ | 功能描述:IC PLL RF FREQ SYNTHESZR 16TSSOP RoHS:是 類別:集成電路 (IC) >> 時鐘/計時 - 時鐘發生器，PLL，頻率合成器 系列:- 標準包裝:2,000 系列:- 類型:PLL 頻率合成器 PLL:是 輸入:晶體 輸出:時鐘 電路數:1 比率 - 輸入:輸出:1:1 差分 - 輸入:輸出:無/無 頻率 - 最大:1GHz 除法器/乘法器:是/無 電源電壓:4.5 V ~ 5.5 V 工作溫度:-20°C ~ 85°C 安裝類型:表面貼裝 封裝/外殼:16-LSSOP（0.175"，4.40mm 寬） 供應商設備封裝:16-SSOP 包裝:帶卷 (TR) 其它名稱:NJW1504V-TE1-NDNJW1504V-TE1TR |
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