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參數(shù)資料
| 型號： | ADF4117BCP |
| 廠商： | ANALOG DEVICES INC |
| 元件分類： | XO, clock |
| 英文描述： | BATT LITHIUM COIN 3V 48MAH COIN-W/LEGS 12.5MM |
| 中文描述： | PLL FREQUENCY SYNTHESIZER, 1200 MHz, CQCC20 |
| 封裝： | CSP-20 |
| 文件頁數(shù)： | 10/20頁 |
| 文件大小： | 226K |
| 代理商： | ADF4117BCP |
ADF4116/ADF4117/ADF4118
–
10
–
REV. 0
PHASE FREQUENCY DETECTOR (PFD) AND CHARGE
PUMP
The PFD takes inputs from the R counter and N counter and
produces an output proportional to the phase and frequency
difference between them. Figure 24 is a simplified schematic.
The PFD includes a fixed delay element which sets the width of
the antibacklash pulse. This is typically 3 ns. This pulse ensures
that there is no dead zone in the PFD transfer function and
gives a consistent reference spur level.
DELAY
U3
CLR1
Q1
D1
CP
DOWN
UP
HI
U1
CLR2
Q2
D2
U2
HI
N DIVIDER
R DIVIDER
V
P
CHARGE
PUMP
CP GND
R DIVIDER
CP OUTPUT
N DIVIDER
Figure 24. PFD Simpli
fi
ed Schematic and Timing (In Lock)
MUXOUT AND LOCK DETECT
The output multiplexer on the ADF4116 family allows the
user to access various internal points on the chip. The state of
MUXOUT is controlled by M3, M2 and M1 in the function
latch. Table VI shows the full truth table. Figure 25 shows the
MUXOUT section in block diagram form.
CONTROL
MUX
DV
DD
MUXOUT
DGND
ANALOG LOCK DETECT
DIGITAL LOCK DETECT
R COUNTER OUTPUT
N COUNTER OUTPUT
SDOUT
Figure 25. MUXOUT Circuit
Lock Detect
MUXOUT can be programmed for two types of lock detect:
Digital Lock Detect and Analog Lock Detect.
Digital Lock Detect is active high. It is set high when the phase
error on three consecutive phase detector cycles is less than 15 ns.
It will stay set high until a phase error of greater than 25 ns is
detected on any subsequent PD cycle.
The N-channel open-drain analog lock detect should be oper-
ated with an external pull-up resistor of 10 k
nominal. When
lock has been detected it is high with narrow low-going pulses.
INPUT SHIFT REGISTER
The ADF4116 family digital section includes a 21-bit input shift
register, a 14-bit R counter and a˙`-bit N counter, comprising
a 5-bit A counter and a 13-bit B counter. Data is clocked into
the 21-bit shift register on each rising edge of CLK. The data is
clocked in MSB first. Data is transferred from the shift register
to one of four latches on the rising edge of LE. The destination
latch is determined by the state of the two control bits (C2, C1)
in the shift register. These are the two LSBs DB1, DB0 as
shown in the timing diagram of Figure 1. The truth table for
these bits is shown in Table VII. Table II shows a summary
of how the latches are programmed.
Table II. C2, C1 Truth Table
Control Bits
C2
C1
Data Latch
0
0
1
1
0
1
0
1
R Counter
N Counter (A and B)
Function Latch
Initialization Latch
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