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參數資料
| 型號： | ADF4153BCP |
| 廠商： | ANALOG DEVICES INC |
| 元件分類： | XO, clock |
| 英文描述： | Fractional-N Frequency Synthesizer |
| 中文描述： | PLL FREQUENCY SYNTHESIZER, 4000 MHz, QCC20 |
| 封裝： | 4 X 4 MM, MO-220VGGD-1, LFCSP-20 |
| 文件頁數： | 18/24頁 |
| 文件大小： | 354K |
| 代理商： | ADF4153BCP |
ADF4153
When a power-down is activated, the following events occur:
Rev. A | Page 18 of 24
1.
All active dc current paths are removed.
2.
The synthesizer counters are forced to their load state
conditions.
3.
The charge pump is forced into three-state mode.
4.
The digital lock detect circuitry is reset.
5.
The RF
IN
input is debiased.
6.
The input register remains active and capable of loading
and latching data.
Lock Detect Precision (LDP)
When this bit is programmed to 0, three consecutive reference
cycles of 15 ns must occur before digital lock detect is set. When
this bit is programmed to 1, five consecutive reference cycles of
15 ns must occur before digital lock detect is set.
Phase Detector Polarity
DB6 in the ADF4153 sets the phase detector polarity. When the
VCO characteristics are positive, this should be set to 1. When
they are negative, it should be set to 0.
Charge Pump Current Setting
DB7, DB8, and DB9 set the charge pump current setting. This
should be set to the charge pump current that the loop filter is
designed with (see Table 9).
REF
IN
Doubler
Setting this bit to 0 feeds the REF
IN
signal directly to the 4-bit
RF R counter, disabling the doubler. Setting this bit to 1
multiplies the REF
IN
frequency by a factor of 2 before feeding
into the 4-bit R counter. When the doubler is disabled, the REF
IN
falling edge is the active edge at the PFD input to the fractional
synthesizer. When the doubler is enabled, both the rising and
falling edges of REF
IN
become active edges at the PFD input.
When the doubler is enabled and the lowest spur mode is
chosen, the in-band phase noise performance is sensitive to the
REF
IN
duty cycle. The phase noise degradation can be as much
as 5 dB for the REF
IN
duty cycles outside a 45% to 55% range.
The phase noise is insensitive to the REF
IN
duty cycle in the
lowest noise mode and in the lowest noise and spur mode. The
phase noise is insensitive to REF
IN
duty cycle when the doubler
is disabled.
NOISE AND SPUR REGISTER, R3
With R3[1, 0] set to 1, 1, the on-chip noise and spur register is
programmed. Table 10 shows the input data format for
programming this register.
Noise and Spur Mode
Noise and spur mode allows the user to optimize a design either
for improved spurious performance or for improved phase
noise performance. When the lowest spur setting is chosen,
dither is enabled. This randomizes the fractional quantization
noise so that it looks more like white noise rather than spurious
noise. This means that the part is optimized for improved
spurious performance. This operation would normally be used
when the PLL closed-loop bandwidth is wide, for fast-locking
applications. (Wide-loop bandwidth is seen as a loop bandwidth
greater than 1/10 of the RF
OUT
channel step resolution (f
RES
)). A
wide-loop filter does not attenuate the spurs to a level that a
narrow-loop bandwidth would. When the low noise and spur
setting is enabled, dither is disabled. This optimizes the
synthesizer to operate with improved noise performance.
However, the spurious performance is degraded in this mode
compared to the lowest spurs setting. To further improve noise
performance, the lowest noise setting option can be used, which
reduces the phase noise. As well as disabling the dither, it also
ensures that the charge pump is operating in an optimum
region for noise performance. This setting is extremely useful
where a narrow-loop filter bandwidth is available. The
synthesizer ensures extremely low noise and the filter attenuates
the spurs. The typical performance characteristics give the user
an idea of the trade-off in a typical WCDMA setup for the
different noise and spur settings.
RESERVED BITS
These bits should be set to 0 for normal operation.
RF SYNTHESIZER: A WORKED EXAMPLE
This equation governs how the synthesizer should be
programmed.
(
OUT
FRAC
INT
RF
+
=
)
[
]
[
×
]
PFD
F
MOD
(3)
where:
RF
OUT
is the RF frequency output.
INT
is the integer division factor.
FRAC
is the fractionality.
MOD
is the modulus.
(
)
[
]
R
D
REF
F
IN
PFD
+
×
=
1
(4)
where:
REF
IN
is the reference frequency input.
D
is the RF REF
IN
doubler bit.
R
is the RF reference division factor.
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相關代理商/技術參數 |
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| ADF4153BCP-REEL | 制造商:Analog Devices 功能描述:PLL Frequency Synthesizer Single 20-Pin LFCSP EP T/R |
| ADF4153BCP-REEL7 | 制造商:Analog Devices 功能描述:PLL Frequency Synthesizer Single 20-Pin LFCSP EP T/R |
| ADF4153BCPZ | 功能描述:IC PLL FREQ SYNTHESIZER 20-LFCSP RoHS:是 類別:集成電路 (IC) >> 時鐘/計時 - 時鐘發生器，PLL，頻率合成器 系列:- 標準包裝:2,000 系列:- 類型:PLL 頻率合成器 PLL:是 輸入:晶體 輸出:時鐘 電路數:1 比率 - 輸入:輸出:1:1 差分 - 輸入:輸出:無/無 頻率 - 最大:1GHz 除法器/乘法器:是/無 電源電壓:4.5 V ~ 5.5 V 工作溫度:-20°C ~ 85°C 安裝類型:表面貼裝 封裝/外殼:16-LSSOP（0.175"，4.40mm 寬） 供應商設備封裝:16-SSOP 包裝:帶卷 (TR) 其它名稱:NJW1504V-TE1-NDNJW1504V-TE1TR |
| ADF4153BCPZ-RL | 功能描述:IC FRACTION-N FREQ SYNTH 20LFCSP RoHS:是 類別:集成電路 (IC) >> 時鐘/計時 - 時鐘發生器，PLL，頻率合成器 系列:- 標準包裝:1,000 系列:Precision Edge® 類型:時鐘/頻率合成器 PLL:無 輸入:CML，PECL 輸出:CML 電路數:1 比率 - 輸入:輸出:2:1 差分 - 輸入:輸出:是/是 頻率 - 最大:10.7GHz 除法器/乘法器:無/無 電源電壓:2.375 V ~ 3.6 V 工作溫度:-40°C ~ 85°C 安裝類型:表面貼裝 封裝/外殼:16-VFQFN 裸露焊盤，16-MLF? 供應商設備封裝:16-MLF?（3x3） 包裝:帶卷 (TR) 其它名稱:SY58052UMGTRSY58052UMGTR-ND |
| ADF4153BCPZ-RL7 | 功能描述:IC FRACTION-N FREQ SYNTH 20LFCSP RoHS:是 類別:集成電路 (IC) >> 時鐘/計時 - 時鐘發生器，PLL，頻率合成器 系列:- 標準包裝:1,000 系列:Precision Edge® 類型:時鐘/頻率合成器 PLL:無 輸入:CML，PECL 輸出:CML 電路數:1 比率 - 輸入:輸出:2:1 差分 - 輸入:輸出:是/是 頻率 - 最大:10.7GHz 除法器/乘法器:無/無 電源電壓:2.375 V ~ 3.6 V 工作溫度:-40°C ~ 85°C 安裝類型:表面貼裝 封裝/外殼:16-VFQFN 裸露焊盤，16-MLF? 供應商設備封裝:16-MLF?（3x3） 包裝:帶卷 (TR) 其它名稱:SY58052UMGTRSY58052UMGTR-ND |
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