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參數資料
| 型號： | ADF4193BCPZ-RL7 |
| 廠商： | ANALOG DEVICES INC |
| 元件分類： | XO, clock |
| 英文描述： | Low Phase Noise, Fast Settling PLL Frequency Synthesizer |
| 中文描述： | PLL FREQUENCY SYNTHESIZER, 3500 MHz, QCC32 |
| 封裝： | 5 X 5 MM, ROHS COMPLIANT, MO-220VHHD-2, LFCSP-32 |
| 文件頁數： | 1/28頁 |
| 文件大小： | 437K |
| 代理商： | ADF4193BCPZ-RL7 |
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Low Phase Noise, Fast Settling PLL
Frequency Synthesizer
ADF4193
FEATURES
New, fast settling, fractional-N PLL architecture
Single PLL replaces ping-pong synthesizers
Frequency hop across GSM band in 5 μs with phase settled
by 20 μs
0.5° rms phase error at 2 GHz RF output
Digitally programmable output phase
RF input range up to 3.5 GHz
3-wire serial interface
On-chip, low noise differential amplifier
Phase noise figure of merit: 216 dBc/Hz
Loop filter design possible using ADI SimPLL
APPLICATIONS
GSM/EDGE base stations
PHS base stations
Instrumentation and test equipment
Rev. B
Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarks and registered trademarks are the property of their respective owners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700
Fax: 781.461.3113
2006 Analog Devices, Inc. All rights reserved.
www.analog.com
GENERAL DESCRIPTION
The ADF4193 frequency synthesizer can be used to implement
local oscillators in the upconversion and downconversion
sections of wireless receivers and transmitters. Its architecture
is specifically designed to meet the GSM/EDGE lock time
requirements for base stations. It consists of a low noise, digital
phase frequency detector (PFD), and a precision differential
charge pump. There is also a differential amplifier to convert
the differential charge pump output to a single-ended voltage
for the external voltage-controlled oscillator (VCO).
The Σ-Δ based fractional interpolator, working with the N
divider, allows programmable modulus fractional-N division.
Additionally, the 4-bit reference (R) counter and on-chip
frequency doubler allow selectable reference signal (REFIN)
frequencies at the PFD input. A complete phase-locked loop
(PLL) can be implemented if the synthesizer is used with an
external loop filter and a VCO. The switching architecture
ensures that the PLL settles inside the GSM time slot guard
period, removing the need for a second PLL and associated
isolation switches. This decreases cost, complexity, PCB area,
shielding, and characterization on previous ping-pong GSM
PLL architectures.
FUNCTIONAL BLOCK DIAGRAM
0
N COUNTER
SW1
CP
OUT+
CP
OUT–
SW2
REFERENCE
DATA
LE
24-BIT
DATA
REGISTER
CLK
REF
IN
A
GND
1
A
GND
2
D
GND
1
D
GND
2
D
GND
3
SD
GND
SW
GND
V
DD
DGND
LOCK DETECT
R
DIV
N
DIV
SDV
DD
DV
DD
1
DV
DD
2
DV
DD
3
AV
DD
1
V
P
1
V
P
2
V
P
3
R
SET
OUTPUT
MUX
MUX
OUT
–
+
HIGH Z
PHASE
FREQUENCY
DETECTOR
ADF4193
FRACTIONAL
INTERPOLATOR
MODULUS
REG
FRACTION
REG
INTEGER
REG
RF
IN+
RF
IN–
×2
DOUBLER
4-BIT R
COUNTER
/2
DIVIDER
CHARGE
PUMP
–
+
+
–
DIFFERENTIAL
AMPLIFIER
CMR
AIN–
AIN+
A
OUT
SW3
Figure 1.
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相關代理商/技術參數 |
參數描述 |
|---|---|
| ADF4193SP1BCPZ | 制造商:Analog Devices 功能描述: |
| ADF4193SP1BCPZ-RL7 | 制造商:Analog Devices 功能描述: |
| ADF4193SP2BCPZ-RL7 | 制造商:Analog Devices 功能描述: |
| ADF4193WCCPZ-RL7 | 功能描述:IC PLL FREQ SYNTHESIZER 32LFCSP RoHS:是 類別:集成電路 (IC) >> 時鐘/計時 - 時鐘發生器，PLL，頻率合成器 系列:- 標準包裝:2,000 系列:- 類型:PLL 時鐘發生器 PLL:帶旁路 輸入:LVCMOS，LVPECL 輸出:LVCMOS 電路數:1 比率 - 輸入:輸出:2:11 差分 - 輸入:輸出:是/無 頻率 - 最大:240MHz 除法器/乘法器:是/無 電源電壓:3.135 V ~ 3.465 V 工作溫度:0°C ~ 70°C 安裝類型:表面貼裝 封裝/外殼:32-LQFP 供應商設備封裝:32-TQFP（7x7） 包裝:帶卷 (TR) |
| ADF4196 | 制造商:AD 制造商全稱:Analog Devices 功能描述:Low Phase Noise, Fast Settling, 6 GHz |
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