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參數(shù)資料
| 型號： | ADF4206BRUZ-RL |
| 廠商： | Analog Devices Inc |
| 文件頁數(shù)： | 1/24頁 |
| 文件大小： | 0K |
| 描述： | IC PLL FREQ SYNTHESIZER 16TSSOP |
| 產(chǎn)品變化通告： | Product Discontinuance 27/Oct/2011 |
| 標(biāo)準(zhǔn)包裝： | 1 |
| 類型： | 時鐘/頻率合成器，RF |
| PLL： | 是 |
| 輸入： | CMOS |
| 輸出： | 時鐘 |
| 電路數(shù)： | 1 |
| 比率 - 輸入:輸出： | 3:1 |
| 差分 - 輸入:輸出： | 是/無 |
| 頻率 - 最大： | 550MHz |
| 除法器/乘法器： | 無/無 |
| 電源電壓： | 2.7 V ~ 5.5 V |
| 工作溫度： | -40°C ~ 85°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 16-TSSOP（0.173"，4.40mm 寬） |
| 供應(yīng)商設(shè)備封裝： | 16-TSSOP |
| 包裝： | 標(biāo)準(zhǔn)包裝 |
| 其它名稱： | ADF4206BRUZ-RLDKR |
Dual RF PLL Frequency Synthesizers
ADF4206/ADF4208
Rev. A
Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibilityis assumedbyAnalogDevicesforitsuse,norforanyinfringements of patents or other
rightsofthirdpartiesthatmayresultfromitsuse.Specificationssubjecttochangewithoutnotice.No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarksandregisteredtrademarksarethepropertyoftheirrespectiveowners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700
www.analog.com
Fax: 781.461.3113
2006 Analog Devices, Inc. All rights reserved.
FEATURES
ADF4206: 550 MHz/550 MHz
ADF4208: 2.0 GHz/1.1 GHz
2.7 V to 5.5 V power supply
Selectable charge pump supply (VP) allows extended
tuning voltage in 3 V systems
Selectable charge pump currents
On-chip oscillator circuit
Selectable dual modulus prescaler
RF2: 32/33 or 64/65
RF1: 32/33 or 64/65
3-wire serial interface
Power-down mode
APPLICATIONS
Wireless handsets (GSM, PCS, DCS, CDMA, WCDMA)
Base stations for wireless radio (GSM, PCS, DCS,
CDMA, WCDMA)
Wireless LANS
Communications test equipment
CATV equipment
GENERAL DESCRIPTION
The ADF420x family of dual frequency synthesizers are used
to implement local oscillators in the upconversion and down-
conversion sections of wireless receivers and transmitters. Each
synthesizer consists of a low noise, digital, phase frequency detector
(PFD); a precision charge pump; a programmable reference
divider; programmable A and B counters; and a dual modulus
prescaler (P/P + 1). The A (6-bit) and B (11-bit) counters, in
conjunction with the dual modulus prescaler (P/P + 1), implement
an N divider (N = BP + A). In addition, the 14-bit reference
counter (R counter) allows selectable REFIN frequencies at the
PFD input. The on-chip oscillator circuitry allows the reference
input to be derived from crystal oscillators.
A complete phase-locked loop (PLL) can be implemented if the
synthesizers are used with an external loop filter and voltage
controlled oscillators (VCOs).
Control of all the on-chip registers is via a simple 3-wire
interface. The devices operate with a power supply ranging
from 2.7 V to 5.5 V and can be powered down when not in use.
FUNCTIONAL BLOCK DIAGRAM
OSCILLATOR
CLK
DATA
LE
22-BIT
DATA
REGISTER
MUXOUT
ADF4206/ADF4208
CPRF1
CPRF2
PHASE
COMPARATOR
OUTPUT
MUX
14-BIT RF2
R-COUNTER
OSCIN
RF1INA
RF1INB
V
DD1
V
DD2
V
P1
V
P2
AGND
RF1
DGND
RF1
DGND
RF2
AGND
RF2
SDOUT
RF2
PRESCALER
RF2INA
11-BIT RF2
B-COUNTER
6-BIT RF2
A-COUNTER
RF2INB
OSCOUT
N= BP + A
CHARGE
PUMP
RF2
LOCK
DETECT
14-BIT RF1
R-COUNTER
RF1
PRESCALER
11-BIT RF1
B-COUNTER
6-BIT RF1
A-COUNTER
N=BP +A
RF1
LOCK
DETECT
PHASE
COMPARATOR
CHARGE
PUMP
01036
-001
Figure 1.
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