- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄373982 > ADF4212BCP (ANALOG DEVICES INC) Dual RF/IF PLL Frequency Synthesizers PDF資料下載
參數(shù)資料
| 型號： | ADF4212BCP |
| 廠商： | ANALOG DEVICES INC |
| 元件分類： | XO, clock |
| 英文描述： | Dual RF/IF PLL Frequency Synthesizers |
| 中文描述： | PLL FREQUENCY SYNTHESIZER, 2700 MHz, QCC20 |
| 封裝： | CSP-20 |
| 文件頁數(shù)： | 5/20頁 |
| 文件大小： | 251K |
| 代理商： | ADF4212BCP |
REV. A
ADF4210/ADF4211/ADF4212/ADF4213
–5–
PIN FUNCTION DESCRIPTIONS
Pin Number
TSSOP
Mnemonic
Function
1
V
DD
1
Power Supply for the RF Section. Decoupling capacitors to the ground plane should be placed as
close as possible to this pin. V
DD
1 should have a value of between 2.7 V and 5.5 V. V
DD
1 must have
the same potential as V
DD
2.
Power Supply for the RF Charge Pump. This should be greater than or equal to V
DD
1. In systems where
V
DD
1 is 3 V, it can be set to 6 V and used to drive a VCO with a tuning range up to 6 V.
Output from the RF Charge Pump. This is normally connected to a loop filter which drives the input
to an external VCO.
Ground Pin for the RF Digital Circuitry.
Input to the RF Prescaler. This low level input signal is ac-coupled from the RF VCO.
Ground Pin for the RF Analog Circuitry.
RF/IF Fastlock Mode.
Reference Input. This is a CMOS input with a nominal threshold of V
DD
/2 and an equivalent input
resistance of 100 k
.
This input can be driven from a TTL or CMOS crystal oscillator.
Digital Ground for the IF Digital, Interface and Control Circuitry.
This multiplexer output allows either the IF/RF Lock Detect, the scaled RF, scaled IF or the scaled
Reference Frequency to be accessed externally.
Serial Clock Input. This serial clock is used to clock in the serial data to the registers. The data is
latched into the 24-bit shift register on the CLK rising edge. This input is a high impedance
CMOS input.
Serial Data Input. The serial data is loaded MSB first with the two LSBs being the control bits. This
input is a high impedance CMOS input.
Load Enable, CMOS Input. When LE goes high, the data stored in the shift registers is loaded into
one of the four latches, the latch being selected using the control bits.
Connecting a resistor between this pin and ground sets the maximum RF and IF charge pump output
current. The nominal voltage potential at the R
SET
pin is 0.66 V. The relationship between I
CP
and R
SET
is
=
13 5
2
V
P
1
3
CP
RF
4
5
6
7
8
DGND
RF
RF
IN
AGND
RF
FL
O
REF
IN
9
10
DGND
IF
MUXOUT
11
CLK
12
DATA
13
LE
14
R
SET
I
R
CP MAX
SET
So, with
R
SET
= 2.7 k
,
I
CP MAX
= 5 mA for both the RF and IF Charge Pumps.
Ground Pin for the IF Analog Circuitry.
Input to the RF Prescaler. This low-level input signal is ac-coupled from the IF VCO.
Ground Pin for the IF Digital, Interface, and Control Circuitry.
Output from the IF Charge Pump. This is normally connected to a loop
fi
lter which drives the input
to an external VCO.
Power Supply for the IF Charge Pump. This should be greater than or equal to V
DD
2. In systems where
V
DD
2 is 3 V, it can be set to 6 V and used to drive a VCO with a tuning range up to 6 V.
Power Supply for the IF, Digital and Interface Section. Decoupling capacitors to the ground plane should
be placed as close as possible to this pin. V
DD
2 should have a value of between 2.7 V and 5.5 V. V
DD
2
must have the same potential as V
DD
1.
15
16
17
18
AGND
IF
IF
IN
DGND
IF
CP
IF
19
V
P
2
20
V
DD
2
PIN CONFIGURATIONS
TSSOP
TOP VIEW
(Not to Scale)
20
19
18
17
16
15
14
13
12
11
1
2
3
4
5
6
7
8
9
10
DATA
CLK
MUXOUT
DGND
RF
RF
IN
AGND
RF
DGND
IF
REF
IN
FL
O
LE
R
SET
AGND
IF
V
DD
1
V
DD
2
V
P
2
CP
IF
IF
IN
DGND
IF
V
P
1
CP
RF
ADF4210/
ADF4211/
ADF4212/
ADF4213
CP-20
1
2
3
4
5
AGND
RF
FL
O
CP
RF
RF
IN
DGND
RF
V
D
2
V
P
2
C
I
16
V
P
1
V
D
1
20
19
18
17
15
14
13
12
11
DGND
IF
IF
IN
LE
R
SET
AGND
IF
6
7 8
9
10
R
I
D
I
M
D
C
TOP VIEW
(Not to Scale)
ADF4210/
ADF4211/
ADF4212/
ADF4213
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| ADF4212BRU | Dual RF/IF PLL Frequency Synthesizers |
| ADF4213 | Dual RF/IF PLL Frequency Synthesizers |
| ADF4213BCP | Dual RF/IF PLL Frequency Synthesizers |
| ADF4213BRU | Dual RF/IF PLL Frequency Synthesizers |
| ADF4216 | Dual RF PLL Frequency Synthesizers |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| ADF4212BRU | 制造商:Analog Devices 功能描述:PLL Frequency Synthesizer Dual 20-Pin TSSOP |
| ADF4212BRU-REEL | 制造商:Analog Devices 功能描述:PLL Frequency Synthesizer Dual 20-Pin TSSOP T/R |
| ADF4212BRU-REEL7 | 制造商:Rochester Electronics LLC 功能描述:DUAL PLL,3.0/0.5GHZ I.C - Tape and Reel |
| ADF4212BRUZ | 功能描述:IC PLL FREQ SYNTHESIZER 20-TSSOP RoHS:是 類別:集成電路 (IC) >> 時鐘/計時 - 時鐘發(fā)生器，PLL，頻率合成器 系列:- 標準包裝:1,000 系列:Precision Edge® 類型:時鐘/頻率合成器 PLL:無 輸入:CML，PECL 輸出:CML 電路數(shù):1 比率 - 輸入:輸出:2:1 差分 - 輸入:輸出:是/是 頻率 - 最大:10.7GHz 除法器/乘法器:無/無 電源電壓:2.375 V ~ 3.6 V 工作溫度:-40°C ~ 85°C 安裝類型:表面貼裝 封裝/外殼:16-VFQFN 裸露焊盤，16-MLF? 供應(yīng)商設(shè)備封裝:16-MLF?（3x3） 包裝:帶卷 (TR) 其它名稱:SY58052UMGTRSY58052UMGTR-ND |
| ADF4212BRUZ-RL | 功能描述:IC PLL FREQ SYNTHESIZER 20-TSSOP RoHS:是 類別:集成電路 (IC) >> 時鐘/計時 - 時鐘發(fā)生器，PLL，頻率合成器 系列:- 標準包裝:1,000 系列:Precision Edge® 類型:時鐘/頻率合成器 PLL:無 輸入:CML，PECL 輸出:CML 電路數(shù):1 比率 - 輸入:輸出:2:1 差分 - 輸入:輸出:是/是 頻率 - 最大:10.7GHz 除法器/乘法器:無/無 電源電壓:2.375 V ~ 3.6 V 工作溫度:-40°C ~ 85°C 安裝類型:表面貼裝 封裝/外殼:16-VFQFN 裸露焊盤，16-MLF? 供應(yīng)商設(shè)備封裝:16-MLF?（3x3） 包裝:帶卷 (TR) 其它名稱:SY58052UMGTRSY58052UMGTR-ND |
發(fā)布緊急采購，3分鐘左右您將得到回復(fù)。