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參數(shù)資料
| 型號： | ADF4360-0 |
| 廠商： | Analog Devices, Inc. |
| 元件分類： | XO, clock |
| 英文描述： | Integrated Synthesizer and VCO |
| 中文描述： | 綜合合成器和VCO |
| 文件頁數(shù)： | 19/24頁 |
| 文件大小： | 539K |
| 代理商： | ADF4360-0 |
ADF4360-5
FIXED FREQUENCY LO
Figure 17 shows the ADF4360-5 used as a fixed frequency LO at
1.4 GHz. The low-pass filter was designed using ADIsimPLL for
a channel spacing of 8 MHz and an open-loop bandwidth of
40 kHz. The maximum PFD frequency of the ADF4360-5 is
8 MHz. Since using a larger PFD frequency allows the use of a
smaller N, the in-band phase noise is reduced to as low as pos-
sible, –101 dBc/Hz. The 40 kHz bandwidth is chosen to be just
greater than the point at which the open-loop phase noise of the
VCO is –101 dBc/Hz, thus, giving the best possible integrated
noise. The typical rms phase noise (100 Hz to 100 kHz) of the
LO in this configuration is 0.33°. The reference frequency is
from a 16 MHz TCXO from Fox; thus an R value of 2 is pro-
grammed. Taking into account the high PFD frequency and its
effect on the band select logic, the band select clock divider is
enabled. In this case, a value of 8 is chosen. A very simple pull-
up resistor and dc blocking capacitor complete the RF output
stage.
Rev. 0 | Page 19 of 24
S
ADF4360-5
V
VCO
C
N
V
VCO
FOX
801BE-160
16MHz
V
VCO
CPGND
AGND
DGNDRF
OUT
B
15
RF
OUT
A
CP
1nF
5.6nF
27.0nF
51
51
51
100pF
100pF
1nF
1nF
10
μ
F
4.7k
3600
R
SET
C
C
LE
DATA
CLK
REF
IN
V
TUNE
DV
DD
AV
DD
CE MUXOUT
5
4
24
7
20
23
2
21
6
14
16
17
18
19
13
1
3
8
9
10
11
22
12
V
VDD
LOCK
DETECT
0
Figure 17. Fixed Frequency LO
POWER-UP
After power-up, the part needs three writes for normal opera-
tion. The correct sequence is to the R counter latch, followed by
the control latch, and N counter latch.
INTERFACING
The ADF4360 family has a simple SPI compatible serial inter-
face for writing to the device. CLK, DATA, and LE control the
data transfer. When LE goes high, the 24 bits that have been
clocked into the appropriate register on each rising edge of CLK
are transferred to the appropriate latch. See Figure 2 for the
timing diagram and Table 5 for the latch truth table.
The maximum allowable serial clock rate is 20 MHz. This
means that the maximum update rate possible is 833 kHz or
one update every 1.2 μs. This is certainly more than adequate
for systems that have typical lock times in hundreds of micro-
seconds.
ADuC812 Interface
Figure 18 shows the interface between the ADF4360 family and
the ADuC812 MicroConverter. Since the ADuC812 is based on
an 8051 core, this interface can be used with any 8051 based
microcontroller. The MicroConverter is set up for SPI master
mode with CPHA = 0. To initiate the operation, the I/O port
driving LE is brought low. Each latch of the ADF4360 family
needs a 24-bit word, which is accomplished by writing three
8-bit bytes from the MicroConverter to the device. When the
third byte has been written, the LE input should be brought
high to complete the transfer.
0
ADuC812
ADF4360-x
SCLK
SDATA
LE
CE
MUXOUT
(LOCK DETECT)
SCLOCK
MOSI
I/O PORTS
Figure 18. ADuC812 to ADF4360-x Interface
I/O port lines on the ADuC812 are also used to control power-
down (CE input) and detect lock (MUXOUT configured as lock
detect and polled by the port input). When operating in the
described mode, the maximum SCLOCK rate of the ADuC812
is 4 MHz. This means that the maximum rate at which the out-
put frequency can be changed is 166 kHz.
ADSP-2181 Interface
Figure 19 shows the interface between the ADF4360 family and
the ADSP-21xx digital signal processor. The ADF4360 family
needs a 24-bit serial word for each latch write. The easiest way
to accomplish this using the ADSP-21xx family is to use the
autobuffered transmit mode of operation with alternate fram-
ing. This provides a means for transmitting an entire block of
serial data before an interrupt is generated.
0
ADSP-21xx
I/O PORTS
ADF4360-x
SCLK
SDATA
LE
CE
MUXOUT
(LOCK DETECT)
SCLOCK
MOSI
TFS
Figure 19. ADSP-21xx to ADF4360-x Interface
Set up the word length for 8 bits and use three memory loca-
tions for each 24-bit word. To program each 24-bit latch, store
the 8-bit bytes, enable the autobuffered mode, and write to the
transmit register of the DSP. This last operation initiates the
autobuffer transfer.
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PDF描述 |
|---|---|
| ADF4360-0BCP | Integrated Synthesizer and VCO |
| ADF4360-0BCPRL | Integrated Synthesizer and VCO |
| ADF4360-6 | Integrated Synthesizer and VCO |
| ADF4360-6BCPRL | Integrated Synthesizer and VCO |
| ADF4360-6BCPRL7 | Integrated Synthesizer and VCO |
相關代理商/技術參數(shù) |
參數(shù)描述 |
|---|---|
| ADF4360-0BCP | 制造商:Analog Devices 功能描述:PLL Frequency Synthesizer Single 24-Pin LFCSP EP 制造商:Rochester Electronics LLC 功能描述:- Bulk 制造商:Analog Devices 功能描述:IC SYNTHESIZER PLL |
| ADF4360-0BCPRL | 制造商:Analog Devices 功能描述:PLL Frequency Synthesizer Single 24-Pin LFCSP EP T/R |
| ADF4360-0BCPRL7 | 制造商:Analog Devices 功能描述:PLL Frequency Synthesizer Single 24-Pin LFCSP EP T/R |
| ADF4360-0BCPZ | 功能描述:IC INTEGRATED SYNTH/VCO 24-LFCSP RoHS:是 類別:集成電路 (IC) >> 時鐘/計時 - 時鐘發(fā)生器，PLL，頻率合成器 系列:- 標準包裝:2,000 系列:- 類型:PLL 頻率合成器 PLL:是 輸入:晶體 輸出:時鐘 電路數(shù):1 比率 - 輸入:輸出:1:1 差分 - 輸入:輸出:無/無 頻率 - 最大:1GHz 除法器/乘法器:是/無 電源電壓:4.5 V ~ 5.5 V 工作溫度:-20°C ~ 85°C 安裝類型:表面貼裝 封裝/外殼:16-LSSOP（0.175"，4.40mm 寬） 供應商設備封裝:16-SSOP 包裝:帶卷 (TR) 其它名稱:NJW1504V-TE1-NDNJW1504V-TE1TR |
| ADF4360-0BCPZ | 制造商:Analog Devices 功能描述:IC FREQ SYNTHESIZER |
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