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參數資料
| 型號： | ADF4360-0BCP |
| 廠商： | ANALOG DEVICES INC |
| 元件分類： | 無繩電話/電話 |
| 英文描述： | Integrated Synthesizer and VCO |
| 中文描述： | TELECOM, CELLULAR, BASEBAND CIRCUIT, QCC24 |
| 封裝： | 4 X 4 MM, MO-220-VGGD-2, LFCSP-24 |
| 文件頁數： | 20/24頁 |
| 文件大小： | 539K |
| 代理商： | ADF4360-0BCP |
ADF4360-5
PCB DESIGN GUIDELINES FOR CHIP SCALE PACKAGE
The leads on the chip scale package (CP-24) are rectangular.
The printed circuit board pad for these should be 0.1 mm
longer than the package lead length and 0.05 mm wider than
the package lead width. The lead should be centered on the pad
to ensure that the solder joint size is maximized.
Rev. 0 | Page 20 of 24
The bottom of the chip scale package has a central thermal pad.
The thermal pad on the printed circuit board should be at least
as large as this exposed pad. On the printed circuit board, there
should be a clearance of at least 0.25 mm between the thermal
pad and the inner edges of the pad pattern to ensure that short-
ing is avoided.
Thermal vias may be used on the printed circuit board thermal
pad to improve thermal performance of the package. If vias are
used, they should be incorporated into the thermal pad at 1.2
mm pitch grid. The via diameter should be between 0.3 mm and
0.33 mm, and the via barrel should be plated with 1 ounce of
copper to plug the via.
The user should connect the printed circuit thermal pad to
AGND. This is internally connected to AGND.
OUTPUT MATCHING
There are a number of ways to match the output of the
ADF4360-5 for optimum operation; the most basic is to use a
50 resistor to V
VCO
. A dc bypass capacitor of 100 pF is con-
nected in series as shown Figure 20. Because the resistor is not
frequency dependent, this provides a good broadband match.
The output power in the circuit below typically gives 4.5 dBm
output power into a 50 load.
100pF
0
RF
OUT
V
VCO
50
51
Figure 20. Simple ADF4360-5 Output Stage
A better solution is to use a shunt inductor (acting as an RF
choke) to V
VCO.
This gives a better match and, therefore, more
output power. Additionally, a series inductor is added after the
dc bypass capacitor to provide a resonant LC circuit. This tunes
the oscillator output and provides approximately 10 dB addi-
tional rejection of the second harmonic. The shunt inductor
needs to be a relatively high value (>40 nH).
Experiments have shown that the circuit shown in Figure 21
provides an excellent match to 50 over the operating range of
the ADF4360-5. This gives approximately 3 dBm output power
across the frequency range of the ADF4360-5. Both single-
ended architectures can be examined using the EVAL-
ADF4360-5EB1 evaluation board.
5.1nH
47nH
3.9pF
0
RF
OUT
V
VCO
50
Figure 21. Optimum ADF4360-5 Output Stage
If the user does not need the differential outputs available on
the ADF4360-5, the user may either terminate the unused out-
put or combine both outputs using a balun. The circuit in
Figure 22 shows how best to combine the outputs.
5.1nH
6.8nH
47nH
6.8nH
2.2pF
10pF
2.2pF
50
5.1nH
RF
OUT
A
V
VCO
RF
OUT
B
0
Figure 22. Balun for Combining ADF4360-5 RF Outputs
The circuit in Figure 22 is a lumped lattice type LC balun. It is
designed for a center frequency of 1.3 GHz and outputs 5.0 dBm
at this frequency. The series 5.1 nH inductor is used to tune out
any parasitic capacitance due to the board layout from each
input, and the remainder of the circuit is used to shift the
output of one RF input by +90° and the second by 90°, thus
combining the two. The action of the 6.8 nH inductor and the
2.2 pF capacitor accomplishes this. The 47 nH is used to provide
an RF choke to feed the supply voltage, and the 10 pF capacitor
provides the necessary dc block. To ensure good RF perform-
ance, the circuits in Figure 21 and Figure 22 are implemented
with Coilcraft 0402/0603 inductors and AVX 0402 thin-film
capacitors.
Alternatively, instead of the LC balun shown in Figure 22, both
outputs may be combined using a 180° rat-race coupler.
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| ADF4360-0BCPRL | 制造商:Analog Devices 功能描述:PLL Frequency Synthesizer Single 24-Pin LFCSP EP T/R |
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| ADF4360-0BCPZ | 功能描述:IC INTEGRATED SYNTH/VCO 24-LFCSP RoHS:是 類別:集成電路 (IC) >> 時鐘/計時 - 時鐘發生器，PLL，頻率合成器 系列:- 標準包裝:2,000 系列:- 類型:PLL 頻率合成器 PLL:是 輸入:晶體 輸出:時鐘 電路數:1 比率 - 輸入:輸出:1:1 差分 - 輸入:輸出:無/無 頻率 - 最大:1GHz 除法器/乘法器:是/無 電源電壓:4.5 V ~ 5.5 V 工作溫度:-20°C ~ 85°C 安裝類型:表面貼裝 封裝/外殼:16-LSSOP（0.175"，4.40mm 寬） 供應商設備封裝:16-SSOP 包裝:帶卷 (TR) 其它名稱:NJW1504V-TE1-NDNJW1504V-TE1TR |
| ADF4360-0BCPZ | 制造商:Analog Devices 功能描述:IC FREQ SYNTHESIZER |
| ADF4360-0BCPZRL | 功能描述:IC SYNTHESIZER VCO 24LFCSP RoHS:是 類別:集成電路 (IC) >> 時鐘/計時 - 時鐘發生器，PLL，頻率合成器 系列:- 標準包裝:1,000 系列:Precision Edge® 類型:時鐘/頻率合成器 PLL:無 輸入:CML，PECL 輸出:CML 電路數:1 比率 - 輸入:輸出:2:1 差分 - 輸入:輸出:是/是 頻率 - 最大:10.7GHz 除法器/乘法器:無/無 電源電壓:2.375 V ~ 3.6 V 工作溫度:-40°C ~ 85°C 安裝類型:表面貼裝 封裝/外殼:16-VFQFN 裸露焊盤，16-MLF? 供應商設備封裝:16-MLF?（3x3） 包裝:帶卷 (TR) 其它名稱:SY58052UMGTRSY58052UMGTR-ND |
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