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參數(shù)資料
| 型號(hào)： | ADF4360-6BCPZRL7 |
| 廠商： | Analog Devices Inc |
| 文件頁(yè)數(shù)： | 1/24頁(yè) |
| 文件大小： | 0K |
| 描述： | IC SYNTHESIZER VCO 24LFCSP |
| 標(biāo)準(zhǔn)包裝： | 1,500 |
| 類(lèi)型： | 扇出配送，整數(shù)-N，合成器（RF） |
| PLL： | 是 |
| 輸入： | CMOS，TTL |
| 輸出： | 時(shí)鐘 |
| 電路數(shù)： | 1 |
| 比率 - 輸入:輸出： | 1:2 |
| 差分 - 輸入:輸出： | 無(wú)/無(wú) |
| 頻率 - 最大： | 1.25GHz |
| 除法器/乘法器： | 是/無(wú) |
| 電源電壓： | 3 V ~ 3.6 V |
| 工作溫度： | -40°C ~ 85°C |
| 安裝類(lèi)型： | 表面貼裝 |
| 封裝/外殼： | 24-VFQFN 裸露焊盤(pán)，CSP |
| 供應(yīng)商設(shè)備封裝： | 24-LFCSP-VQ（4x4） |
| 包裝： | 帶卷 (TR) |
| 配用： | EVAL-ADF4360-6EBZ1-ND - BOARD EVALUATION FOR ADF4360-6 |
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Integrated Synthesizer and VCO
Data Sheet
Rev. B
InformationfurnishedbyAnalogDevicesisbelievedtobeaccurateandreliable.However,nore-
sponsibilityisassumedbyAnalogDevicesforitsuse,norforanyinfringementsofpatentsorother
rightsofthirdpartiesthatmayresultfromitsuse.Specificationssubjecttochangewithoutnotice.No
licenseisgrantedbyimplicationorotherwiseunderanypatentorpatentrightsofAnalogDevices.
Trademarksandregisteredtrademarksarethepropertyoftheirrespectiveowners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700
2003–2012 Analog Devices, Inc. All rights reserved.
FEATURES
Output frequency range: 1050 MHz to 1250 MHz
Divide-by-2 output
3.0 V to 3.6 V power supply
1.8 V logic compatibility
Integer-N synthesizer
Programmable dual-modulus prescaler 8/9, 16/17, 32/33
Programmable output power level
3-wire serial interface
Analog and digital lock detect
Hardware and software power-down mode
APPLICATIONS
Wireless handsets (DECT, GSM, PCS, DCS, WCDMA)
Test equipment
Wireless LANs
CATV equipment
GENERAL DESCRIPTION
The ADF4360-6 is a fully integrated integer-N synthesizer and
voltage-controlled oscillator (VCO). The ADF4360-6 is de-
signed for a center frequency of 1150 MHz. In addition, a di-
vide-by-2 option is available, whereby the user receives an RF
output of between 525 MHz and 625 MHz.
Control of all the on-chip registers is through a simple 3-wire
interface. The device operates with a power supply ranging from
3.0 V to 3.6 V and can be powered down when not in use.
FUNCTIONAL BLOCK DIAGRAM
MUXOUT
CP
VVCO
REFIN
CLK
DATA
LE
AVDD
DVDD
CE
AGND
DGND
CPGND
RSET
VTUNE
CC
CN
RFOUTA
RFOUTB
VCO
CORE
PHASE
COMPARATOR
MUTE
DIVSEL = 2
DIVSEL = 1
N = (BP + A)
LOAD
CHARGE
PUMP
OUTPUT
STAGE
M
U
L
T
IPL
EXER
INTEGER
REGISTER
13-BIT B
COUNTER
14-BIT R
COUNTER
24-BIT
FUNCTION
LATCH
24-BIT
DATA REGISTER
5-BIT A
COUNTER
PRESCALER
P/P+1
MULTIPLEXER
LOCK
DETECT
2
ADF4360-6
04440-001
Figure 1.
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