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參數(shù)資料
型號(hào): ADG3241BRY-REEL7
廠商: ANALOG DEVICES INC
元件分類: 通用總線功能
英文描述: 2.5 V/3.3 V, 1-Bit, 2-Port Level Translator Bus Switch in SOT-66
中文描述: 3241 SERIES, 1-BIT DRIVER, TRUE OUTPUT, PDSO6
封裝: SOT-66, 6 PIN
文件頁(yè)數(shù): 4/12頁(yè)
文件大?。?/td> 213K
代理商: ADG3241BRY-REEL7
REV. A
–4–
ADG3241
TERMINOLOGY
V
CC
GND
V
INH
V
INL
I
I
I
OZ
I
OL
V
P
Positive Power Supply Voltage.
Ground (0 V) Reference.
Minimum Input Voltage for Logic 1.
Maximum Input Voltage for Logic 0.
Input Leakage Current at the Control Inputs.
OFF State Leakage Current. It is the maximum leakage current at the switch pin in the OFF state.
ON State Leakage Current. It is the maximum leakage current at the switch pin in the ON state.
Maximum Pass Voltage. The maximum pass voltage relates to the clamped output voltage of an NMOS device when
the switch input voltage is equal to the supply voltage.
Ohmic Resistance Offered by a Switch in the ON State. It is measured at a given voltage by forcing a specified
amount of current through the switch.
OFF Switch Capacitance.
ON Switch Capacitance.
Control Input Capacitance. This consists of
BE
and
SEL
.
Quiescent Power Supply Current. This current represents the leakage current between the V
CC
and ground pins.
It is measured when all control inputs are at a logic high or low level and the switches are OFF.
Extra power supply current component for the
BE
control input when the input is not driven at the supplies.
Data Propagation Delay through the Switch in the ON State. Propagation delay is related to the RC time constant
R
ON
×
C
L
, where C
L
is the load capacitance.
Bus Enable Times. These are the times taken to cross the V
T
voltage at the switch output when the switch turns on
in response to the control signal,
BE
.
Bus Disable Times. This is the time taken to place the switch in the high impedance OFF state in response to the control
signal. It is measured as the time taken for the output voltage to change by V from the original quiescent level,
with reference to the logic level transition at the control input. (Refer to Figure 3 for enable and disable times.)
Maximum Rate at which Data Can Be Passed through the Switch.
Peak-to-Peak Value of the Sum of the Deterministic and Random Jitter of the Switch Channel.
R
ON
C
X
OFF
C
X
ON
C
IN
I
CC
I
CC
t
PLH
, t
PHL
t
PZH
, t
PZL
t
PHZ
, t
PLZ
Max Data Rate
Channel Jitter
PIN CONFIGURATION
6-Lead SC70
1
GND
A
V
CC
B
BE
SEL
ADG3241
TOP VIEW
(Not to Scale)
2
3
6
5
4
6-Lead SOT-66
1
SEL
A
B
GND
V
CC
BE
ADG3241
TOP VIEW
(Not to Scale)
2
3
6
5
4
Table II. Pin Function Descriptions
Pin No.
SC70
1
2
3
4
5
6
SOT-66
6
4
3
5
1
2
Mnemonic
BE
GND
A
B
V
CC
SEL
Description
Bus Enable (Active Low)
Ground Reference
Port A, Input or Output
Port B, Input or Output
Positive Power Supply Voltage
Level Translation Select
ORDERING GUIDE
Temperature
Range
–40
°
C to +85
°
C
–40
°
C to +85
°
C
–40
°
C to +85
°
C
–40
°
C to +85
°
C
Package
Description
Model
Package
Branding
ADG3241BKS-REEL
ADG3241BKS-REEL7
ADG3241BKS-500RL7
ADG3241BRY-REEL7
Thin Shrink Small Outline Transistor Package (SC70)
Thin Shrink Small Outline Transistor Package (SC70)
Thin Shrink Small Outline Transistor Package (SC70)
Small Outline Transistor Package (SOT-66)
KS-6
KS-6
KS-6
RY-6-1
SKA
SKA
SKA
00
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