
ADG466/ADG467
–8–
REV. A
When a negative overvoltage is applied to the channel protector
circuit, the PMOS transistor enters a saturated mode of opera-
tion as the drain voltage exceeds V
SS
– V
TP
. See Figure 20 be-
low. As in the case of the positive overvoltage, the other MOS
devices are nonsaturated.
NMOS
PMOS
NMOS
V
DD
(+15V)
V
SS
(–15V)
V
DD
(+15V)
NEGATIVE
OVERVOLTAGE
(–20V)
V
SS
– V
TP
*
(–13V)
*V
TP
= PMOS THRESHOLD VOLTAGE (–2V)
NEGATIVE
OVERVOLTAGE
(–20V)
NON-
SATURATED
NON-
SATURATED
SATURATED
Figure 20. Negative Overvoltage on the Channel Protector
The channel protector is also functional when the supply rails
are down (e.g., power failure) or momentarily unconnected
(e.g., rack system). This is where the channel protector has an
advantage over more conventional protection methods such as
diode clamping (see Applications Information). When V
DD
and
V
SS
equal 0 V, all transistors are off and the current is limited to
subnano-ampere levels (see Figure 21).
NMOS
PMOS
NMOS
V
DD
(0V)
V
SS
(0V)
V
DD
(0V)
PNEGATIVE
OVERVOLTAGE
(0V)
OFF
OFF
OFF
Figure 21. Channel Protector Supplies Equal to Zero Volts
TRENCH ISOLATION
The MOS devices that make up the channel protector are iso-
lated from each other by an oxide layer (trench) (see Figure 22).
When the NMOS and PMOS devices are not electrically iso-
lated from each other, there exists the possibility of “l(fā)atch-up”
caused by parasitic junctions between CMOS transistors. Latch-
up is caused when P-N junctions that are normally reverse bi-
ased become forward biased, causing large currents to flow,
which can be destructive.
CMOS devices are normally isolated from each other by
Junc-
tion Isolation
. In Junction Isolation, the
N
and
P
wells of the
CMOS transistors form a diode that is reverse-biased under
normal operation. However, during overvoltage conditions, this
diode becomes forward biased. A Silicon-Controlled Rectifier
(SCR) type circuit is formed by the two transistors causing a
significant amplification of the current that, in turn, leads to
latch-up. With Trench Isolation, this diode is removed; the
result is a latch-up proof circuit.
V
G
V
D
P-CHANNEL
P+
P+
V
S
N–
V
G
V
D
N-CHANNEL
N+
N+
V
S
P–
T
R
E
N
C
H
T
R
E
N
C
H
T
R
E
N
C
H
BURIED OXIDE LAYER
SUBSTRATE (BACKGATE)
Figure 22. Trench Isolation