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參數資料
| 型號： | ADG509FTQ |
| 廠商： | ANALOG DEVICES INC |
| 元件分類： | 運動控制電子 |
| 英文描述： | 4/8 Channel Fault-Protected Analog Multiplexers |
| 中文描述： | 4-CHANNEL, DIFFERENTIAL MULTIPLEXER, CDIP16 |
| 封裝： | CERDIP-16 |
| 文件頁數： | 3/12頁 |
| 文件大小： | 170K |
| 代理商： | ADG509FTQ |
ADG508F/ADG509F/ADG528F
REV. C
–3–
Table I. ADG508F Truth Table
A2
X
0
0
0
0
1
1
1
1
A1
X
0
0
1
1
0
0
1
1
A0
X
0
1
0
1
0
1
0
1
EN
0
1
1
1
1
1
1
1
1
ON SWITCH
NONE
1
2
3
4
5
6
7
8
X = Don’t Care
Table II. ADG509F Truth Table
A1
X
0
0
1
1
A0
X
0
1
0
1
EN
0
1
1
1
1
ON SWITCH PAIR
NONE
1
2
3
4
X = Don’t Care
Table III. ADG528F Truth Table
ON
SWITCH
A2
A1
A0
EN
WR
RS
X
X
X
0
0
0
0
1
1
1
1
X
X
X
0
0
1
1
0
0
1
1
X
X
X
0
1
0
1
0
1
0
1
X
X
0
1
1
1
1
1
1
1
1
g
X
0
0
0
0
0
0
0
0
0
1
0
1
1
1
1
1
1
1
1
1
Retains Previous Switch Condition
NONE (Address and Enable Latches Cleared)
NONE
1
2
3
4
5
6
7
8
X = Don’t Care
TIMING DIAGRAMS (ADG528F)
t
W
50%
50%
t
S
t
H
0.8V
2V
3V
WR
0V
3V
0V
A0, A1, A2
EN
Figure 1.
Figure 1 shows the timing sequence for latching the switch
address and enable inputs. The latches are level sensitive; there-
fore, while
WR
is held low, the latches are transparent and the
switches respond to the address and enable inputs. This input
data is latched on the rising edge of
WR
.
t
RS
t
OFF
(
RS
)
50%
50%
0.8V
O
3V
RS
0V
V
O
SWITCH
OUTPUT
0V
Figure 2.
Figure 2 shows the Reset Pulsewidth, t
RS
, and the Reset Turn-
off Time, t
OFF
(
RS
).
Note: All digital input signals rise and fall times are measured
from 10% to 90% of 3 V. t
R
= t
F
= 20 ns.
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相關代理商/技術參數 |
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|---|---|
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