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參數資料
| 型號： | ADG728BRU |
| 廠商： | ANALOG DEVICES INC |
| 元件分類： | 運動控制電子 |
| 英文描述： | Tantalum Conformal-Coated Capacitor; Capacitance: 220uF; Voltage: 4V; Packaging: Tape & Reel |
| 中文描述： | 8-CHANNEL, AUDIO/VIDEO SWITCH, PDSO16 |
| 封裝： | TSSOP-16 |
| 文件頁數： | 9/12頁 |
| 文件大小： | 150K |
| 代理商： | ADG728BRU |
ADG728/ADG729
–9–
REV. 0
GENERAL DESCRIPTION
The ADG728 and ADG729 are serially controlled, 8-channel
and dual 4-channel matrix switches respectively. While provid-
ing the normal multiplexing and demultiplexing functions, these
devices also provide the user with more flexibility as to where
their signal may be routed. Each bit of the serial word corre-
sponds to one switch of the device. A Logic 1 in the particular
bit position turns on the switch, while a Logic 0 turns the switch
off. Because each switch is independently controlled by an indi-
vidual bit, this provides the option of having any, all, or none of
the switches ON. This feature may be particularly useful in the
demultiplexing application where the user may wish to direct
one signal from the drain to a number of outputs (sources). Care
must be taken, however, in the multiplexing situation where a
number of inputs may be shorted together (separated only by
the small on resistance of the switch).
When changing the switch conditions, a new 8-bit word is writ-
ten to the input shift register. Some of the bits may be the same
as the previous write cycle, as the user may not wish to change
the state of some switches. In order to minimize glitches on the
output of these switches, the part cleverly compares the state of
switches from the previous write cycle. If the switch is already
in the ON condition, and is required to stay ON, there will be
minimal glitches on the output of the switch.
POWER-ON RESET
On power-up of the device, all switches will be in the OFF con-
dition and the internal shift register is filled with zeros and will
remain so until a valid write takes place.
SERIAL INTERFACE
2-Wire Serial Bus
The ADG728/ADG729 are controlled via an I
2
C compatible
serial bus. These parts are connected to this bus as a slave device
(no clock is generated by the multiplexer).
The ADG728/ADG729 have different 7-bit slave addresses.
The five MSBs of the ADG728 are 10011, while the MSBs of
the ADG729 are 10001 and the two LSBs are determined by
the state of the A0 and A1 pins.
The 2-wire serial bus protocol operates as follows:
1. The master initiates data transfer by establishing a START
condition which is when a high-to-low transition on the SDA
line occurs while SCL is high. The following byte is the
address byte, which consists of the 7-bit slave address fol-
lowed by a R/
W
bit (this bit determines whether data will be
read from or written to the slave device).
The slave whose address corresponds to the transmitted
address responds by pulling the SDA line low during the
ninth clock pulse (this is termed the Acknowledge bit). At
this stage, all other devices on the bus remain idle while the
selected device waits for data to be written to or read from its
serial register. If the R/W bit is high, the master will read
from the slave device. However, if the R/
W
bit is low, the
master will write to the slave device.
2. Data is transmitted over the serial bus in sequences of nine
clock pulses (eight data bits followed by an acknowledge bit).
The transitions on the SDA line must occur during the low
period of SCL and remain stable during the high period of
SCL.
3. When all data bits have been read or written, a STOP condition
is established by the master. A STOP condition is defined as
a low-to-high transition on the SDA line while SCL is high.
In Write mode, the master will pull the SDA line high during
the 10th clock pulse to establish a STOP condition. In Read
mode, the master will issue a No Acknowledge for the ninth
clock pulse (i.e., the SDA line remains high). The master will
then bring the SDA line low before the tenth clock pulse and
then high during the tenth clock pulse to establish a STOP
condition.
See Figures 18 to 21 below for a graphical explanation of the
serial interface.
A repeated write function gives the user flexibility to update the
matrix switch a number of times after addressing the part only
once. During the write cycle, each data byte will update the con-
figuration of the switches. For example, after the matrix switch
has acknowledged its address byte, and receives one data byte,
the switches will update after the data byte, if another data byte
is written to the matrix switch while it is still the addressed slave
device, this data byte will also cause an switch configuration
update. Repeat read of the matrix switch is also allowed.
INPUT SHIFT REGISTER
The input shift register is eight bits wide. Figure 15 illustrates
the contents of the input shift register. Data is loaded into the
device as an 8-bit word under the control of a serial clock input,
SCL. The timing diagram for this operation is shown in Figure 1.
The 8-bit word consists of eight data bits each controlling one
switch. MSB (Bit 7) is loaded first.
S8
S7
S6
S5
S4
S3
S2
S1
DB0 (LSB)
DB7 (MSB)
DATA BITS
Figure 15. ADG728/ADG729 Input Shift Register Contents
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| ADG728BRU-REEL7 | 功能描述:IC MUX/DEMUX 8X1 16TSSOP RoHS:否 類別:集成電路 (IC) >> 接口 - 模擬開關，多路復用器，多路分解器 系列:- 標準包裝:1,000 系列:- 功能:多路復用器 電路:1 x 4:1 導通狀態電阻:- 電壓電源:雙電源 電壓 - 電源，單路/雙路(±):±5V 電流 - 電源:7mA 工作溫度:-40°C ~ 85°C 安裝類型:表面貼裝 封裝/外殼:16-SOIC（0.154"，3.90mm 寬） 供應商設備封裝:16-SOIC 包裝:帶卷 (TR) |
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