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參數資料
| 型號： | ADG732BSU |
| 廠商： | ANALOG DEVICES INC |
| 元件分類： | 運動控制電子 |
| 英文描述： | 16-/32- Channel, 3.5 з 1.8 V to 5.5 V, 【2.5 V, Analog Multiplexers |
| 中文描述： | 32-CHANNEL, SGL ENDED MULTIPLEXER, PQFP48 |
| 封裝： | PLASTIC, MS-026BBC, TQFP-48 |
| 文件頁數： | 5/13頁 |
| 文件大小： | 201K |
| 代理商： | ADG732BSU |
–5–
REV. PrD
ADG726/ADG732
PRELIMINARY TECHNICAL DATA
TIMING CHARACTERISTICS
1,2, 3
Parameter
Limit at T
MIN
, T
MAX
0
0
20
10
5
2
Units
Conditions/Comments
t
1
t
2
t
3
t
4
t
5
t
6
ns min
ns min
ns min
ns min
ns min
ns min
to
to
pulse width
Time between
Address, Enable Setup Time
Address, Enable Hold Time
Setup Time
Hold Time
cycles
NOTES
1
See Figure 1.
2
All input signals are specified with tr =tf = 5ns (10% to 90% of V
DD
) and timed from a voltage level of (V
IL
+ V
IH
)/2.
3
Guaranteed by design and characterisation, not production tested.
Specifications subject to change without notice.
Figure 1. Timing Diagram
Figure 1 shows the timing sequence for latching the switch address and enable inputs. The latches are level sensitive;
therefore, while
is held low, the latches are transparent and the switches respond to the address and enable inputs.
This input data is latched on the rising edge of
. The ADG726 has two
either as a dual 16-1 channel multiplexer or a differential 16 channel multiplexer. If a differential output is required, tie
and
together.
inputs. This enables the part to be used
A0, A1, A2, A3, (A4)
EN
t
6
t
5
WR
t
3
CS
t
1
t
2
t
4
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