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參數資料
| 型號： | ADG812YRU-REEL |
| 廠商： | ANALOG DEVICES INC |
| 元件分類： | 運動控制電子 |
| 英文描述： | 0.5 CMOS 1.65 V to 3.6 V Quad SPST Switches |
| 中文描述： | QUAD 1-CHANNEL, SGL POLE SGL THROW SWITCH, PDSO16 |
| 封裝： | MO-153AB, TSSOP-16 |
| 文件頁數： | 7/16頁 |
| 文件大小： | 392K |
| 代理商： | ADG812YRU-REEL |
ADG811/ADG812/ADG813
PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
Rev. A | Page 7 of 16
NC = NO CONNECT
NC
D1
S1
IN1
IN4
S4
D4
GND
D2
S2
VDD
IN2
S3
D3
IN3
NC
TOP VIEW
(Not to Scale)
ADG811/
ADG812/
ADG813
4
2
3
1
8
6
7
5
15
14
13
16
11
10
9
12
0
Figure 2.
Table 7. Terminology
Term
V
DD
I
DD
GND
S
D
IN
V
D
, V
S
R
ON
R
FLAT (ON)
Definition
Most positive power supply potential.
Positive supply current.
Ground (0 V) reference.
Source terminal. May be an input or output.
Drain terminal. May be an input or output.
Logic control input.
Analog voltage on Terminals D, S.
Ohmic resistance between D and S.
Flatness is defined as the difference between the maximum and minimum value of on resistance as measured over the
specified analog signal range.
On resistance match between any two channels, i.e., R
ON
max – R
ON
min.
Source leakage current with the switch off.
Drain leakage current with the switch off.
Channel leakage current with the switch on.
Maximum input voltage for Logic 0.
Minimum input voltage for Logic 1.
Input current of the digital input.
Off switch source capacitance. Measured with reference to ground.
Off switch drain capacitance. Measured with reference to ground.
On switch capacitance. Measured with reference to ground.
Digital input capacitance.
Delay time between the 50% and the 90% points of the digital input and switch on condition.
Delay time between the 50% and the 90% points of the digital input and switch off condition.
On or off time measured between the 80% points of both switches, when switching from one to another.
A measure of the glitch impulse transferred from the digital input to the analog output during on-to-off switching.
A measure of unwanted signal coupling through an off switch.
A measure of unwanted signal that is coupled through from one channel to another as a result of parasitic capacitance.
The frequency at which the output is attenuated by 3 dB.
The frequency response of the on switch.
The loss due to the on resistance of the switch.
The ratio of the harmonic amplitudes plus noise of a signal to the fundamental.
R
ON
I
S
(OFF)
I
D
(OFF)
I
D
, I
S
(ON)
V
INL
V
INH
I
INL
(I
INH
)
C
S
(OFF)
C
D
(OFF)
C
D
, C
S
(ON)
C
IN
t
ON
t
OFF
t
BBM
Charge Injection
Off Isolation
Crosstalk
–3 dB Bandwidth
On Response
Insertion Loss
THD + N
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