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參數資料
| 型號： | ADG820 |
| 廠商： | Analog Devices, Inc. |
| 英文描述： | 0.5 OHM CMOS 1.8 V to 5.5 V 2:1 Mux/SPDT Switches |
| 中文描述： | 0.5歐姆的CMOS 1.8 V至5.5 V 2:1復用/ SPDT開關 |
| 文件頁數： | 5/12頁 |
| 文件大小： | 195K |
| 代理商： | ADG820 |
REV. 0
ADG819/ADG820
–5–
CAUTION
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate
on the human body and test equipment and can discharge without detection. Although the ADG819/
ADG820 features proprietary ESD protection circuitry, permanent damage may occur on devices
subjected to high energy electrostatic discharges. Therefore, proper ESD precautions are recommended
to avoid performance degradation or loss of functionality.
WARNING!
ESD SENSITIVE DEVICE
TERMINOLOGY
V
DD
GND
I
DD
S
D
IN
R
ON
R
ON
R
FLAT(ON)
Most Positive Power Supply Potential
Ground (0 V) Reference
Positive Supply Current
Source Terminal. May be an input or output.
Drain Terminal. May be an input or output.
Logic Control Input
Ohmic Resistance between D and S
ON Resistance Match between Any Two Channels, i.e., R
ON
max – R
ON
min
Flatness is defined as the difference between the maximum and minimum value of ON resistance as
measured over the specified analog signal range.
Source Leakage Current with the Switch OFF
Channel Leakage Current with the Switch ON
Analog Voltage on Terminals D, S
Maximum Input Voltage for Logic “0”
Minimum Input Voltage for Logic “1”
Input Current of the Digital Input
OFF Switch Source Capacitance
ON Switch Capacitance
Delay between applying the digital control input and the output switching ON.
Delay between applying the digital control input and the output switching OFF.
OFF time or ON time measured between the 90% points of both switches when switching
from one address state to another.
ON time measured between the 80% points of both switches when switching from one
address state to another.
A measure of the glitch impulse transferred from the digital input to the analog output during switching.
A measure of unwanted signal coupled through from one channel to another as a result of parasitic
capacitance.
A measure of unwanted signal coupling through an OFF switch.
Frequency at which the output is attenuated by –3 dB.
Frequency Response of the ON Switch
Loss due to the ON Resistance of the Switch
I
S
(OFF)
I
D
, I
S
(ON)
V
D
(V
S
)
V
INL
V
INH
I
INL
(I
INH
)
C
S
(OFF)
C
D
, C
S
(ON)
t
ON
t
OFF
t
BBM
t
MBB
Charge Injection
Crosstalk
OFF Isolation
Bandwidth
ON Response
Insertion Loss
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| ADG820BRT | 制造商:AD 制造商全稱:Analog Devices 功能描述:0.5 OHM CMOS 1.8 V to 5.5 V 2:1 Mux/SPDT Switches |
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