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參數(shù)資料
| 型號： | ADL5519ACPZ-R2 |
| 廠商： | ANALOG DEVICES INC |
| 元件分類： | 運動控制電子 |
| 英文描述： | 1 MHz to 10 GHz, 50 dB Dual Log Detector/Controller |
| 中文描述： | DUAL LOG OR ANTILOG AMPLIFIER, 10000 MHz BAND WIDTH, QCC32 |
| 封裝： | 5 X 5 MM, ROHS COMPLIANT, MO-220VHHD-2, LFCSP-32 |
| 文件頁數(shù)： | 7/27頁 |
| 文件大小： | 479K |
| 代理商： | ADL5519ACPZ-R2 |
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Preliminary Technical Data
ADL5519
Parameter
Input B to OUTA Isolation
OUTPUT INTERFACE
OUT[A, B] Voltage Range Min
OUT[P, N] output
OUT[P, N] Voltage Range Min
Source/Sink Current
Small Signal Bandwidth
Output Noise
Rev. PrB | Page 7 of 27
Conditions
P
INHB
= 50 dBm, OUTB = OUTB
PINHB
± 1 dB
P
INHA
= 50 dBm, OUTA = OUTA
PINHA
± 1 dB
OUT[A, B] (Pins 12, 7), OUT[P, N] (Pins 10, 9)
VST[A, B] = TBD RFIN = open RL
≥
240
Ω
to ground
VST[A, B] = 0V RFIN = open RL
≥
240
Ω
to ground
OUT[A, B] = OUT[P, N]
FBK[A, B] = TBD RFIN = open RL
≥
240
Ω
to ground
FBK[A, B] = 0V RFIN = open RL
≥
240
Ω
to ground
Output held at 1V to 1% change
RFIN = 10 dBm, from CLP[A,B] to OUT[A,B]
RF Input = 2.2 GHz, –10 dBm, f
NOISE
= 100 kHz,
C
LP[A,B]
= open
Input level = no signal to –10 dBm, 90% to 10%,
C
LP[A,B]
= 8 pF
Input level = no signal to –10 dBm, 90% to 10%,
C
LP[A,B]
= open;
Input level = 10 dBm to no signal, 10% to 90%,
C
LP[A, B]
= 8 pF
Input level = 10 dBm to no signal, 10% to 90%,
C
LP[A,B]
= open,
Min
Typ
TBD
TBD
TBD
TBD
VLVL
TBD
TBD
2.2
TBD
TBD
Max
Unit
dB
dB
V
V
V
V
mA
MHz
nV/
√
Hz
Fall Time
TBD
ns
Fall Time
TBD
ns
Rise Time
TBD
ns
Rise Time
TBD
ns
Video Bandwidth (or Envelope
Bandwidth)
SETPOINT INTERFACE
Nominal Input Range
Logarithmic Scale Factor
Logarithmic Intercept
Input Resistance
50
MHz
VST[A, B] (Pins 13, 6)
Input level = 0 dBm, measurement mode
Input level = –50 dBm, measurement mode
Input level = 20 dBm, controller mode, VST[A,B] = 1
V
VLVL (Pin 4)
OUT[P, N] = FBK[A, B]
OUT[P, N] = FBK[A, B]
ADJ[A, B] (Pins 17, 2)
ADJ[A, B] = 0.9 V, sourcing 50 μA
ADJ[A, B] = open
VREF (Pin 3)
40
°
C < T
A
< +85
°
C
TEMP (Pin 15)
40
°
C < T
A
< +125
°
C
Pin PWDN
Logic LO enables
Logic HI disables
Logic HI PWDN = 5 V
Logic LO PWDN = 0 V
PWDN LO to OUTA/OUTB at 100% final value,
C
LPA/B
= Open, C
HPA/B
= 10 nF, RF in = 0 dBm
0.5
1.75
45
TBD
40
V
V
dB/V
k
Ω
DIFFERENCE LEVEL ADJUST
Voltage Range
OUT[P, N] Voltage Range
Input Impedance
TEMPERATURE COMPENSATION
Input Resistance
Disable Threshold Voltage
VOLTAGE REFERENCE
Output Voltage
Temperature Sensitivity
Current Limit Source/Sink
TEMPERATURE REFERENCE
Output Voltage
Temperature Sensitivity
Current Limit Source/Sink
POWER-DOWN INTERFACE
Logic Level to Enable
Logic Level to Disable
Input Current
Enable Time
TBD
TBD
TBD
13
V
POS
– 0.4
1.15
TBD
3/3
1.3
4.5
5/40
TBD
TBD
TBD
TBD
TBD
V
V
Ω
||pF
k
Ω
V
V
mV/
o
C
mA
V
mV/
o
C
mA/uA
V
V
μA
μA
μs
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