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參數(shù)資料
| 型號(hào)： | ADM1023ARQ |
| 廠商： | ANALOG DEVICES INC |
| 元件分類： | 模擬信號(hào)調(diào)理 |
| 英文描述： | ACPI-Compliant High-Accuracy Microprocessor System Temperature Monitor |
| 中文描述： | SPECIALTY ANALOG CIRCUIT, PDSO16 |
| 封裝： | MO-137AB, QSOP-16 |
| 文件頁數(shù)： | 2/12頁 |
| 文件大小： | 170K |
| 代理商： | ADM1023ARQ |
–2–
REV. A
ADM1023–SPECIFICATIONS
(T
A
= T
MIN
to T
MAX1
, V
DD
= 3.0 V to 3.6 V, unless otherwise noted)
Parameter
Min
Typ
Max
Unit
Test Conditions/Comments
POWER SUPPLY AND ADC
Temperature Resolution, Local Sensor
Temperature Resolution, Remote Sensor
Temperature Error, Local Sensor
1
0.125
–1.5
–3
–1
–3
°
C
°
C
°
C
°
C
°
C
°
C
°
C
V
V
mV
V
mV
μ
A
μ
A
μ
A
μ
A
ms
Guaranteed No Missed Codes
Guaranteed No Missed Codes
T
A
= 60
°
C to 100
°
C
T
A
= 0
°
C to 120
°
C
T
A
, T
D
= 60
°
C to 100
°
C (Note 2)
T
A
, T
D
= 0
°
C to 120
°
C (Note 2)
T
A
= 60
°
C to 100
°
C
Note 3
V
DD
Input, Disables ADC, Rising Edge
±
0.5
±
1
+1.5
+3
+1
+3
0.25
3.6
2.8
Temperature Error, Remote Sensor
Relative Accuracy
Supply Voltage Range
Undervoltage Lockout Threshold
Undervoltage Lockout Hysteresis
Power-On Reset Threshold
POR Threshold Hysteresis
Standby Supply Current
3
2.55
2.7
25
1.7
50
1
4
130
225
115
0.9
2.2
V
DD
, Falling Edge (Note 4)
5
V
DD
= 3.3 V, No SMBus Activity
SCLK at 10 kHz
0.25 Conversions/Sec Rate
2 Conversions/Sec Rate
From Stop Bit to Conversion
Complete (Both Channels)
D+ Forced to D– + 0.65 V
High Level (Note 4)
Low Level (Note 4)
Average Operating Supply Current
Autoconvert Mode, Averaged Over 4 Sec
Conversion Time
200
330
170
65
Remote Sensor Source Current
120
7
205
12
0.7
50
300
16
μ
A
μ
A
V
μ
A
D-Source Voltage
Address Pin Bias Current (ADD0, ADD1)
Momentary at Power-On Reset
SMBus INTERFACE
Logic Input High Voltage, V
IH
STBY
, SCLK, SDATA
Logic Input Low Voltage, V
IL
STBY
, SCLK, SDATA
SMBus Output Low Sink Current
ALERT
Output Low Sink Current
Logic Input Current, I
IH
, I
IL
SMBus Input Capacitance, SCLK, SDATA
SMBus Clock Frequency
SMBus Clock Low Time, t
LOW
SMBus Clock High Time, t
HIGH
SMBus Start Condition Setup Time, t
SU:STA
SMBus Start Condition Hold Time, t
HD:STA
2.2
V
V
DD
= 3 V to 5.5 V
0.8
V
V
DD
= 3 V to 5.5 V
6
1
–1
mA
mA
μ
A
pF
kHz
μ
s
ns
ns
ns
SDATA Forced to 0.6 V
ALERT
Forced to 0.4 V
+1
5
100
4.7
4
4.7
4
t
LOW
Between 10% Points
t
HIGH
Between 90% Points
Time from 10% of SDATA to 90%
of SCLK
Time from 90% of SCLK to 10%
of SDATA
Time for 10% or 90% of
SDATA to 10% of SCLK
SMBus Stop Condition Setup Time, t
SU:STO
4
ns
SMBus Data Valid to SCLK
Rising Edge Time, t
SU:DAT
SMBus Data Hold Time, t
HD:DAT
SMBus Bus Free Time, t
BUF
SCLK Falling Edge to SDATA
Valid Time, t
VD,DAT
SMBus Leakage Current
250
ns
0
4.7
μ
s
μ
s
μ
s
Between Start/Stop Condition
Master Clocking in Data
1
5
μ
A
V
DD
= 0 V
NOTES
1
T
MAX
= 120
°
C, T
MIN
= 0
°
C
.
2
T
, T
= 60
°
C to 100
°
C.
3
Operation at V
= 5 V guaranteed by design, not production tested.
4
Guaranteed by design, not production tested.
Specifications subject to change without notice.
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