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參數資料
| 型號： | ADM1033 |
| 廠商： | ANALOG DEVICES INC |
| 元件分類： | 模擬信號調理 |
| 英文描述： | Thermal Monitor and Fan Speed (RPM) Controller |
| 中文描述： | SPECIALTY ANALOG CIRCUIT, PDSO16 |
| 封裝： | QSOP-16 |
| 文件頁數： | 15/40頁 |
| 文件大小： | 1164K |
| 代理商： | ADM1033 |
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ADM1033
READ OPERATIONS
Receive Byte
Rev. 0 | Page 15 of 40
This operation is useful when repeatedly reading a single
register. The register address must be set up prior to this, with
the MSB at 0 to read a single byte. In this operation, the master
device receives a single byte from a slave device as follows:
1.
The master device asserts a start condition on SDA.
2.
The master sends the 7-bit slave address followed by the
read bit (high).
3.
The addressed slave device asserts ACK on SDA.
4.
The master receives a data byte.
5.
The master sends NO ACK on SDA.
6.
The master asserts a stop condition on SDA and the
transaction ends.
In the ADM1033, the receive-byte protocol is used to read a
single byte from a register whose address has previously been
set by a send-byte or write-byte operation.
SLAVE
ADDRESS
S
DATA
R A
A P
0
Figure 24. Receive Byte
Block Read
In this operation, the master reads a block of data from a slave
device. The number of bytes to be read must be set in advance.
To do this, use
a write-byte operation to the #Bytes/Block Read
Register at Address 0x00. The register address determines
whether a block-read or a read-byte operation is to be
completed (set MSB to 1 to specify a block-read operation). A
maximum number of 32 bytes can be read.
1.
The master asserts a start condition on SDA.
2.
The master sends the 7-bit slave address followed by the
write bit (low).
3.
The addressed slave device asserts ACK on SDA.
4.
The master sends the register address (MSB = 1).
5.
The slave asserts ACK on SDA.
6.
The master asserts a repeated start on SDA.
7.
The master sends the 7-bit slave address followed by the
read bit (high).
8.
The slave asserts ACK on SDA.
9.
The slave sends the byte count.
10.
The master asserts ACK on SDA.
11.
The slave sends N data bytes.
12.
The master asserts ACK on SDA after each data byte.
13.
The master does not acknowledge after the Nth data byte.
14.
The master asserts a stop condition on SDA to end the
transaction.
SLAVE
ADDRESS
S
BYTE
COUNT
DATA 1
REGISTER
ADDRESS
W
A
P
A
A
A DATA N
SLAVE
ADDRESS
S
R
A
0
A
Figure 25. Block Read from RAM
SMBus TIMEOUT
The ADM1033 has a programmable SMBus timeout feature.
When this is enabled, the SMBus typically times out after 25 ms
of no activity. The timeout is disabled by default. It prevents
SMBus hangups by releasing the bus after a period of inactivity.
To enable the SDA timeout, set the SDA timeout bit (Bit 5) of
Configuration Register 1 (Address 0x01) to 1.
To enable the SCL timeout, set the SCL timeout bit (Bit 4) of
Configuration Register 1 (Address 0x01) to 1.
PACKET ERROR CHECKING (PEC)
The ADM1033 supports packet error checking (PEC). This
optional feature is triggered by the extra clock for the PEC byte.
The PEC byte is calculated using CRC-8. The frame check
sequence (FCS) conforms to CRC-8 by the following:
1
)
(
2
8
+
+
+
=
x
x
x
x
C
For more information, consult www.SMBus.org.
ALERT RESPONSE ADDRESS (ARA)
ALERT RESPONSE
ADDRESS
S
DEVICE
ADDRESS
R A
A P
0
Figure 26. Alert Response Address
When multiple devices exist on the same bus, the alert response
address (ARA) feature allows an interrupting device to identify
itself to the host. The ALERT output can be used as an interrupt
output or as an SMBALERT. One or more ALERT outputs can
be connected to a common SMBALERT line, which is
connected to the master. If a device’s ALERT line goes low, the
following procedure occurs:
1.
SMBALERT is pulled low.
2.
The master initiates a receive-byte operation and sends the
alert response address (ARA 0001 100). This is a general call
address that must not be used as a specific device address.
3.
The device with the low ALERT output responds to the
ARA, and the master reads its device address. Once the
address is known, it can be interrogated in the usual way.
4.
If low ALERToutput is detected in more than one device,
the one with the lowest device address has priority, in
accordance with normal SMBus arbitration.
5.
Once the ADM1033 has responded to the ARA, it resets its
ALERT output. If the error persists, the ALERT is re-
asserted on the next monitoring cycle.
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