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參數(shù)資料
| 型號： | ADM1033ARQ |
| 廠商： | Analog Devices, Inc. |
| 英文描述： | Thermal Monitor and Fan Speed (RPM) Controller |
| 中文描述： | 熱監(jiān)測和風(fēng)扇轉(zhuǎn)速（RPM）控制器 |
| 文件頁數(shù)： | 30/40頁 |
| 文件大小： | 1164K |
| 代理商： | ADM1033ARQ |
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ADM1033
PROGRAMMING THE THERM LIMIT FOR
TEMPERATURE CHANNELS
THERM is the absolute maximum temperature allowed on a
temperature channel. Above this temperature, a component
such as the CPU or VRM might operate beyond its safe
operating limit. When the temperature exceeds THERM, all fans
are driven at full speed to provide critical system cooling. The
fans remain running at 100% until the temperature drops below
THERM Hysteresis. The hysteresis value can be pro-
grammed; its default is 5°C. If the boost disable bit (Bit 1) is set
in Configuration Register 2, the fans do not run to full speed.
Rev. 0 | Page 30 of 40
The THERM limit is considered the maximum worst-case
operating temperature of the system. Exceeding any THERM
limit runs all fans at full speed, a condition with very negative
acoustic effects. This limit should be set up as a fail-safe and not
exceeded under normal system operating conditions. The
THERM temperature limit registers are listed in Table 32.
Table 32. THERM Hysteresis Registers
Address
Description
0x0D
Local THERM Limit
0x10
Remote THERM Limit
Default
0x95 (85°C)
0x95 (85°C)
The THERM hysteresis register is at Address 0x1A. A value is
programmed and applied to both temperature channels—local
and remote. A THERM hysteresis value of between 0°C and
15°C can be programmed with a resolution of 1°C. See Table 33.
Table 33. Programming THERM Hysteresis
Code
Hysteresis Value
0000 0000
0°C
0000 0001
1°C
0000 0010
2°C
0000 0101
5°C
0000 1000
8°C
0000 1111
15°C
XOR TREE TEST MODE
The ADM1033 includes an XOR tree test mode. This mode
is useful for in-circuit test equipment at board-level testing.
By applying stimulus to the pins included in the XOR test, it
is possible to detect opens or shorts on the system board.
Figure 43 shows the signals exercised in this mode.
FAN_FAULT/REF
TACH1
ALERT_COMP
THERM
ALERT
LOCATION
DRIVE1
0
Figure 43. XOR Tree Test
LOCK BIT
Setting the lock bit (Bit 6) of Configuration Register 1 (Address
0x01) makes all the lockable registers read-only. These registers
remain read only until the ADM1033 is powered down and
back up again. For more information on which registers are
lockable, see Table 33.
SW RESET
Setting the software reset bit (Bit 0) of Configuration Register 1
(Address 0x01) resets all software-resettable bits to their default
value. For more information on resetting registers and their
default values, see Table 34 to Table 68.
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