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| 型號： | ADM1060 |
| 廠商： | Analog Devices, Inc. |
| 英文描述： | DIP Socket; No. of Contacts:56; Pitch Spacing:0.07"; Row Spacing:0.6"; Terminal Type:PC Board; Leaded Process Compatible:Yes; Peak Reflow Compatible (260 C):No RoHS Compliant: Yes |
| 中文描述： | 通信系統(tǒng)監(jiān)控/排序電路 |
| 文件頁數(shù)： | 8/45頁 |
| 文件大小： | 303K |
| 代理商： | ADM1060 |
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ADM1060
ADM1060 INPUTS
–
8
–
REV. PrJ 11/02
PRELIMINARY TECHNICAL DATA
T hus, N=192 (11000000 or C0H)
T he available threshold ranges, and the resolution they are
programmed to are shown in table 1. Note that the low
end of the detection range is fixed to 33.33% of the top of
the range. Note also, that for a given SFD, the ranges
overlap (eg) VH goes from 2V to 6V then from 4.8V to
14.4V. T his is to provide better threshold setting resolu-
tion as supplies decrease in value.
Input Name
Voltage Ranges
Resolution
V H
4.8V to 14.4V
2V to 6V
2V to 6V
1V to 3V
-6V to -2V
2V to 6V
1V to 3V
0.6V to 1.8V
37.6mV
15.6mV
15.6mV (Pos. Mode)
7.8mV
15.6mV (Neg. Mode)
15.6mV
7.8mV
4.7mV
V Bn
“
VPn
Table 1. Input threshold Ranges and Resolution
.
Figure 2 illustrates the function of the programmable
SFD (for the case of a positive supply).
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Figure 2. Positive Programmable Supply Fault Detector
SFD COMPARAT OR HY ST E RE SIS
T he OV and UV comparators, shown in figure 1, are al-
ways looking at VPn via a potential divider. In order to
avoid chattering (multiple transitions when the input is
very close to the threshold level set), these comparators
have digitally progammable hysteresis. T he UV and OV
hysteresis can be programmed in two registers which are
similar but separate to the UV or OV threshold registers.
Only the 5 LSB
’
s of these registers can be set. T he
hysteresis is added after the supply voltage goes out of
tolerance. T hus, the user can determine how much above
the UV threshold the input must rise again before a UV
fault is de-asserted. Similarly, the user can determine
how much below the OV threshold the input must fall
again before an OV fault is de-asserted. T he hysteresis
figure is given by:-
V
H
=V
R
x N
THRESH
/255
where:-
V
H
= Desired Hysteresis Voltage
N
T HRESH
= Decimalized version of 5 bit hysteresis code
T herefore, if the low range threshold detector was selected
(ie) 1V to 3V (V
R
), the max hysteresis is then defined as:-
(3V-1V) x 31/255 = 242mV (2
5
-1 =31)
T he hysteresis programming resolution is the same as the
threshold detect ranges (ie) 37.5mV on the high range,
15.6mV on the mid range, 7.8mV on the low range and
4.7mV on the ultra low range.
BIPOLAR SFD
’
S
T he 2 bipolar SFD
’
s also allow the detection of faults on
negative supplies. A polarity bit in the setup register for
this SFD (bit 7- register BSnSEL- see register map
overleaf) determines if a positive or negative input should
be applied to VBn. Only 1 range (-6V to -2V) is available
when the SFD
’
s are in negative mode. Note that the bi-
polar SFD
’
s cannot be used to power the ADM1060, even
if the voltage on VBn is positive.
SFD FAULT T Y PE S
3 types of faults can be asserted by the SFD- 1) An OV
fault, 2) an UV fault and 3) an out-of-window fault (where
the UV and OV faults are OR
’
ed together). T he type of
fault required is programmed using the Fault T ype Select
bits (bits 0,1- Register _SnSEL). If an application re-
quires separate fault conditions to be detected on one sup-
ply (eg) assert PDO1 if an UV fault occurs on a 3.3V
supply, assert PDO9 if an OV fault occurs on the same
3.3V supply, that supply will need to be applied to more
than one input pin.
GLIT CH FILT E RING ON T HE SFD
’
S
T he final stage of the SFD is a glitch filter. T his block
provides time domain filtering on spurious transitions of
the SFD fault output. T hese could be caused by bounce
on a supply at its initial turn- on. T he comparators of the
SFD can have hysteresis digitally programmed into them
to ensure smooth transitions but further deglitching is
provided by the glitch filter stage. A fault must be as-
serted for greater than the programmed Glitch Filter
timeout before it is seen at the output of the glitch filter.
T he max. programmable timeout period is 100 s. Both
edges of the input are filtered by the same amount of time,
so if the input pulse is longer than the glitch filter timeout
and is seen at the output, the length of the output pulse is
the same as the input pulse. If the input pulse is shorter
than the programmed timeout, then nothing appears at the
output. Figure 2 shows the implementation of glitch fil-
tering.
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