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參數資料
| 型號： | ADM1060ARU |
| 廠商： | ANALOG DEVICES INC |
| 元件分類： | 電源管理 |
| 英文描述： | CON-HDR64POS2ROW 4WALL.1X.1SP,RTANG,LOPF |
| 中文描述： | 7-CHANNEL POWER SUPPLY MANAGEMENT CKT, PDSO28 |
| 封裝： | MO-153AE, TSSOP-28 |
| 文件頁數： | 14/45頁 |
| 文件大小： | 303K |
| 代理商： | ADM1060ARU |
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ADM1060
ADM1060 INPUTS
–
14
–
REV. PrJ 11/02
PRELIMINARY TECHNICAL DATA
WA T C H D OG F A UL T D E T E C T OR
T he ADM1060 has a Watchdog Fault Detector. T his can
be used to monitor a processor clock to ensure normal
operation. T he detector monitors the WDI pin, expecting
there to be a low-to-high or high to low transition within a
preprogrammed period. T he watchdog timeout period
can be programmed from 200msec to a maximum of
12.8sec.
If no transition is detected, 2 signals are asserted. One is
a latched high signal, indicating a fault has occurred. T he
other signal is a low- high- low pulse which can be used as
a RESET signal for a processor core. T he width of this
pulse can be programmed (from 10 s to a maximum of
10ms). T hese two Watchdog signals can be selected as
inputs to each of the PLB
’
s (see PLBA section). T hey
T ABL E 18. L IST OF RE GIST E RS F OR WAT C HD OG F AUL T D E T E C T OR
Hex
T able
Name
Address
D efault
Power On Value
Description
9C
19
W D C F G
00h
Program length Watchdog timeout and length of pulsed output
T ABL E 19. RE GIST E R 9C H WDC F G (POWE R- ON DE F AUL T 00H)
Bit
Name
R/W
Description
7-5
Reserved
R /W
Unused
4-3
PU L S1-PU L S0
R /W
Length of pulse outputted once the Watchdog Detector has timed out
P U L S 1
P U L S 0
Pulse L ength Selected (
0
0
10
0
1
100
1
0
1000
1
1
10000
s)
2-0
PE R3-PE R0
R /W
Watchdog T imeout Period
P E R 2
P E R 1
P E R 0
Watchdog T imeout selected (ms)
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
D isabled
200
400
800
1600
3200
6400
12800
can also be inverted, if required (eg) if a high- low- high
pulse was required by a processor to reset. T hus, a fault
on the watchdog can be used to generate a pulsed or
latched output on any or all of the 9 PDO
’
s.
T he latched signal can be cleared low by reading LAT F1,
then LAT F2 across the SMBus interface (see Fault Regis-
ters section). T he RAM register list and the bit map for
the Watchdog Fault Detector are shown below.
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