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參數資料
| 型號： | ADM1060ARU |
| 廠商： | ANALOG DEVICES INC |
| 元件分類： | 電源管理 |
| 英文描述： | CON-HDR64POS2ROW 4WALL.1X.1SP,RTANG,LOPF |
| 中文描述： | 7-CHANNEL POWER SUPPLY MANAGEMENT CKT, PDSO28 |
| 封裝： | MO-153AE, TSSOP-28 |
| 文件頁數： | 5/45頁 |
| 文件大小： | 303K |
| 代理商： | ADM1060ARU |
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–5–
REV.PrJ 11/02
ADM1060–SPECIFICATIONS
1
PRELIMINARY TECHNICAL DATA
NOT E S
1
T hese are target specifications and subject to change.
2
At least one supply connected to VH or VPn must be >=3.0V
3
L ogic inputs will accept input high voltages up to 5.5V even when device is operating at supply voltages below 5V.
4
T iming specifications are tested at logic levels of V
IL
= 0.8V for a falling edge and V
IH
= 2.2V for a rising edge.
PROGRAMMABLE DRIVE R
OUT PUT S
High Voltage (Charge Pump) Mode
(PDO’s 1 to 4)
Output Impedance, R
OUT
V
O H
440
12.5
12
20
k
V
V
10.5
10
14
I
OH
= 0
I
OH
=1 A
2V <V
OH
<7V
I
OU T AV G
Standard (Digital Output) Mode
(PDO’s 1 to 9)
V
O H
A
2.4
V
V
PU
(Pullup to VDDCAP or
VPn)=2.7V, I
OH
=1mA
V
PU
to VPn=6.0V, I
OH
=0mA
VPU<=2.7V, I
OH
=1mA
I
OL
=2mA
I
OL
=10mA
I
OL
=15mA
T otal Sink Current
Internal pullup
Current Load on any VPn pull-ups
(ie) total source current available
through any number of PDO pull-up
switches configured on to any one
V
PD O
=14.4V
4.5
V
V
V
V
V
mA
k
mA
V
PU
-0.3
V
OL
0.4
1.2
2.0
20
I
SINK
R
PU L L U P-
I
SOURC E (VPn)
Weak Pull-up
20
2
T ristate Output L eakage Current
DIGIT AL INPUT S
(GPI 1-4,WDI,A0,A1)
Input High Voltage, V
IH
Input Low Voltage, V
IL
Input High Current, I
IH
Input Low Current, I
IL
Input C apacitance
Programmable Pulldown C urrent, I
PUL L DOWN
SE RIAL BUS DIGIT AL INPUT S
(SD A,SC L )
Input High Voltage, V
IH
Input Low Voltage, V
IL
Output Low Voltage, V
OL
PROGRAMMABLE DE LAY BLOCK
T imeout
10
A
2.0
V
V
Max. V
IN
=5.5V
Max. V
IN
=5.5V
V
IN
= 5.5V
V
IN
= 0
0.8
-1
A
A
1
T BD
10
pF
A
If known logic state required
2.0
V
V
V
0.8
0.4
I
OUT
= -3.0mA
0
500
ms
16 programmable options on both
rising and falling edge
WAT CHDOG T IME R INPUT
T imeout
0
12.8
s
8 programmable timeout options
SE RIAL BUS T IMING
C lock Frequency, f
SC L K
Glitch Immunity, t
SW
Bus Free T ime, t
BUF
Start Setup T ime, t
SU;ST A
Start Hold T ime, t
HD;ST A
SCL L ow T ime, t
L OW
SC L High T ime, t
HIGH
SCL, SDA Rise T ime, t
r
SCL, SDA Fall T ime, t
f
Data Setup T ime, t
SU;DAT
Data Hold T ime, t
HD;DAT
400
50
K H z
ns
μs
μs
μs
μs
μs
ns
μs
ns
ns
See Figure 8c
See Figure 8c
See Figure 8c
See Figure 8c
See Figure 8c
See Figure 8c
See Figure 8c
See Figure 8c
See Figure 8c
See Figure 8c
See Figure 8c
4.7
4.7
4
4.7
4
1000
300
250
300
(VH=4.5V to 14.4V, VPn = 3.0V to 6.0V
2
, T
A
= -40
o
C to 85
o
C, unless otherwse noted.)
Parameter
Min
T yp
Max
Units
T est C onditions/C omments
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