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參數(shù)資料
| 型號： | ADM1088 |
| 廠商： | Analog Devices, Inc. |
| 英文描述： | Simple Sequencers in 6-Lead SC70 |
| 中文描述： | 簡單排序6引腳SC70 |
| 文件頁數(shù)： | 9/16頁 |
| 文件大小： | 299K |
| 代理商： | ADM1088 |
ADM1085/ADM1086/ADM1087/ADM1088
CIRCUIT INFORMATION
TIMING CHARACTERISTICS AND TRUTH TABLES
The enable outputs of the ADM1085/ADM1086/ADM1087/
ADM1088 are related to the V
IN
and enable inputs by a simple
AND function. The enable output is asserted only if the enable
input is asserted and the voltage at V
IN
is above V
TH_RISING
, with
the time delay elapsed. Table 5 and Table 6 show the enable
output logic states for different V
IN
/enable input combinations
when the capacitor delay has elapsed. The timing diagrams in
Figure 18 and Figure 19 give a graphical representation of how
the ADM1085/ADM1086/ADM1087/ADM1088 enable outputs
respond to V
IN
and enable input signals.
Table 5. ADM1085/ADM1086 Truth Table
V
IN
ENIN
<V
TH_FALLING
0
<V
TH_FALLING
1
>V
TH_RISING
0
>V
TH_RISING
1
Table 6. ADM1087/ADM1088 Truth Table
V
IN
ENIN
<V
TH_FALLING
1
<V
TH_FALLING
0
>V
TH_RISING
1
>V
TH_RISING
0
Rev. 0 | Page 9 of 16
ENOUT
0
0
0
1
ENOUT
1
1
1
0
0
V
IN
ENIN
ENOUT
t
EN
V
TH_RISING
V
TH_FALLING
Figure 18. ADM1085/ADM1086 Timing Diagram
0
V
IN
ENIN
ENOUT
t
EN
V
TH_RISING
V
TH_FALLING
Figure 19. ADM1087/ADM1088 Timing Diagram
When V
IN
reaches the upper threshold voltage (V
TH_RISING
), an
internal circuit generates a delay (t
EN
) before the enable output
is asserted. If V
IN
drops below the lower threshold voltage
(V
TH_FALLING
), the enable output is deasserted immediately.
Similarly, if the enable input is disabled while V
IN
is above the
threshold, the enable output deasserts immediately. Unlike V
IN
, a
low-to-high transition on ENIN (or high-to-low on ENIN) does
not yield a time delay on ENOUT (ENOUT).
CAPACITOR-ADJUSTABLE DELAY CIRCUIT
Figure 20 shows the internal circuitry used to generate the time
delay on the enable output. A 250 nA current source charges a
small internal parasitic capacitance, C
INT
. When the capacitor
voltage reaches 1.2 V, the enable output is asserted. The time
taken for the capacitor to reach 1.2 V, in addition to the propa-
gation delay of the comparator, constitutes the enable timeout,
which is typically 35 μs.
To minimize the delay between V
IN
falling below V
TH_FALLING
and
the enable output de-asserting, an NMOS transistor is con-
nected in parallel with C
INT
. The output of the voltage detector
is connected to the gate of this transistor so that, when V
IN
falls
below V
TH_FALLING
, the transistor switches on and C
INT
discharges
quickly.
0
1.2V
C
C
INT
CEXT
SIGNAL FROM
VOLTAGE
DETECTOR
TO AND GATE
AND OUTPUT
STAGE
V
CC
250nA
Figure 20. Capacitor-Adjustable Delay Circuit
Connecting an external capacitor to the CEXT pin delays the
rise time—and therefore the enable timeout—further. The
relationship between the value of the external capacitor and the
resulting timeout is characterized by the following equation:
t
EN
= (
C
× 4.8 ×10
6
) + 35 μs
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