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參數資料
| 型號： | ADM1185ARMZ-1REEL7 |
| 廠商： | ANALOG DEVICES INC |
| 元件分類： | 電源管理 |
| 英文描述： | Quad Voltage Monitor and Sequencer |
| 中文描述： | 4-CHANNEL POWER SUPPLY SUPPORT CKT, PDSO10 |
| 封裝： | ROHS COMPLIANT, MO-187BA, MSOP-10 |
| 文件頁數： | 5/16頁 |
| 文件大小： | 270K |
| 代理商： | ADM1185ARMZ-1REEL7 |
ADM1185
PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
Rev. 0 | Page 5 of 16
GND
1
VIN1
2
VIN2
3
VIN3
4
VIN4
5
VCC
10
OUT1
9
OUT2
8
OUT3
7
PWRGD
6
ADM1185
TOP VIEW
(Not to Scale)
0
Figure 3.
Table 4. Pin Function Descriptions
Pin No.
Mnemonic
1
GND
2
VIN1
Description
Chip Ground Pin.
Noninverting Input of Comparator 1. The voltage on this pin is compared with a 0.6 V reference. Can be used to
monitor a voltage rail via a resistor divider. The output of this comparator is monitored by the state machine core.
This input can also be driven by a logic signal to initiate a power-up sequence.
Noninverting Input of Comparator 2. The voltage on this pin is compared with a 0.6 V reference. Can be used to
monitor a voltage rail via a resistor divider. The output of this comparator is monitored by the state machine core.
Noninverting Input of Comparator 3. The voltage on this pin is compared with a 0.6 V reference. Can be used to
monitor a voltage rail via a resistor divider. The output of this comparator is monitored by the state machine core.
Noninverting Input of Comparator 4. The voltage on this pin is compared with a 0.6 V reference. Can be used to
monitor a voltage rail via a resistor divider. The output of this comparator is monitored by the state machine core.
Active-High, Open-Drain Output. This output is pulled low once VCC = 1 V. When the voltage on each VINx input
exceeds 0.6 V, the state machine moves from STATE4 to STATE5, and PWRGD is asserted. Once in State 5 (the
PWRGD state), this output is driven low if the voltage on VIN1, VIN2, VIN3, or VIN4 falls below 0.6 V.
Active-High, Open-Drain Output. This output is pulled low once VCC = 1 V. When the voltage on VIN3 exceeds 0.6 V,
the state machine moves from STATE3 to STATE4, and OUT3 is asserted. Once the power-up sequence is complete
and STATE5 (the PWRGD state) is reached, this output is driven low if the voltage on VIN1 falls below 0.6 V.
Active-High, Open-Drain Output. This output is pulled low once VCC = 1 V. When the voltage on VIN2 exceeds 0.6 V,
the state machine moves from STATE2 to STATE3, and OUT2 is asserted. Once the power-up sequence is complete
and STATE5 (the PWRGD state) is reached, this output is driven low if the voltage on VIN1 falls below 0.6 V.
Active-High, Open-Drain Output. This output is pulled low once VCC = 1 V. When the voltage on VIN1 exceeds 0.6 V,
the state machine moves from STATE1 to STATE2, and OUT1 is asserted. A time delay of 190 ms (typical) is included
before the assertion of this pin. Once the power-up sequence is complete and STATE5 (the PWRGD state) is
reached, this output is driven low if the voltage on VIN1 falls below 0.6 V.
Positive Supply Input Pin. The operating supply voltage range is 2.7 V to 5.5 V.
3
VIN2
4
VIN3
5
VIN4
6
PWRGD
7
OUT3
8
OUT2
9
OUT1
10
VCC
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