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參數資料
| 型號： | ADM13305-5ARZ1 |
| 廠商： | Analog Devices, Inc. |
| 英文描述： | Dual Processor Supervisors with Watchdog |
| 中文描述： | 雙處理器監控器，帶有看門狗 |
| 文件頁數： | 5/12頁 |
| 文件大小： | 214K |
| 代理商： | ADM13305-5ARZ1 |
ADM13305
TIMING REQUIREMENTS
V
DD
= 2.7 V to 5.5 V, R
L
= 1 MΩ, C
L
= 50 pF, T
A
= 25°C.
Rev. 0 | Page 5 of 12
Table 3. ADM13305-18, ADM13305-25 and ADM13305-33
Parameter
Min
PULSE WIDTH (t
w
)
SENSEv
6
MR
100
WDI
100
Typ
Max
Unit
μs
ns
ns
Test Conditions/Comments
V
SENSEvL
= V
IT
0.3 V, V
SENSEvH
= V
IT+
+ 0.3 V
V
IH
= 0.7 × V
DD
, V
IL
= 0.3 × V
DD
V
IH
= 0.7 × V
DD
, V
IL
= 0.3 × V
DD
Table 4. ADM13305-4 and ADM13305-5
Parameter
PULSE WIDTH (t
w
)
SENSEv
MR
WDI
Min
100
100
Typ
30
Max
Unit
μs
ns
ns
Test Conditions/Comments
V
SENSEvL
= V
IT
0.3 V, V
SENSEvH
= V
IT+
+ 0.3 V
V
IH
= 0.7 × V
DD
, V
IL
= 0.3 × V
DD
V
IH
= 0.7 × V
DD
, V
IL
= 0.3 × V
DD
SWITCHING CHARACTERISTICS
V
DD
= 2.7 V to 5.5 V, R
L
= 1 MΩ, C
L
= 50 pF, T
A
= 25°C.
Table 5. ADM13305-18, ADM13305-25 and ADM13305-33
Parameter
Watchdog Timeout (t
t(OUT)
)
Delay Time (t
d
)
Propagation Delay, High-to-Low, MR to RESET
1
/RESET (t
PHL
)
Propagation Delay, Low-to-High, MR to RESET/RESET
1
(t
PLH
)
Propagation Delay, High-to-Low, SENSEv to RESET
1
/RESET (t
PHL
)
Propagation Delay, Low-to-High, SENSEv to RESET/RESET
1
(t
PLH
)
Min
1.1
140
Typ
1.6
200
200
200
1
1
Max
2.3
280
500
500
5
5
Unit
sec
ms
ns
ns
μs
μs
Test Conditions/Comments
V
I(SENSEv)
≥ V
IT+
+ 0.2 V, MR ≥ 0.7 × V
DD
V
I(SENSEv)
≥ V
IT+
+ 0.2 V, MR ≥ 0.7 × V
DD
V
I(SENSEv)
≥ V
IT+
+ 0.2 V, V
IH
≥ 0.7 × V
DD
, V
IL
≥ 0.3 × V
DD
V
I(SENSEv)
≥ V
IT+
+ 0.2 V, V
IH
≥ 0.7 × V
DD
, V
IL
≥ 0.3 × V
DD
V
IH
= V
IT+
+ 0.3 V, V
IL
= V
IT
0.3 V, MR ≥ 0.7 × V
DD
V
IH
= V
IT+
+ 0.3 V, V
IL
= V
IT
0.3 V, MR ≥ 0.7 × V
DD
1
The reset timeout delay of 200 ms masks the propagation delay.
Table 6. ADM13305-4 and ADM13305-5
Parameter
Watchdog Timeout (t
t(out)
)
Delay Time (t
d
)
Propagation Delay, High-to-Low, MR to RESET
1
/RESET (t
PHL
)
Propagation Delay, Low-to-High, MR to RESET/RESET
1
(t
PLH
)
Propagation Delay, High-to-Low, SENSEv to RESET
1
/RESET (t
PHL
)
Propagation Delay, Low-to-High, SENSEv to RESET/RESET
1
(t
PLH
)
Min
1.1
140
Typ
1.6
200
200
200
30
30
Max
2.3
280
500
500
Unit
sec
ms
ns
ns
μs
μs
Test Conditions/Comments
V
I(SENSEv)
≥ V
IT+
+ 0.2 V, MR ≥ 0.7 × V
DD
V
I(SENSEv)
≥ V
IT+
+ 0.2 V, MR ≥ 0.7 × V
DD
V
I(SENSEv)
≥ V
IT+
+ 0.2 V, V
IH
≥ 0.7 × V
DD
, V
IL
≥ 0.3 × V
DD
V
I(SENSEv)
≥ V
IT+
+ 0.2 V, V
IH
≥ 0.7 × V
DD
, V
IL
≥ 0.3 × V
DD
V
IH
= V
IT+
+ 0.3 V, V
IL
= V
IT
0.3 V, MR ≥ 0.7 × V
DD
V
IH
= V
IT+
+ 0.3 V, V
IL
= V
IT
0.3 V, MR ≥ 0.7 × V
DD
1
The reset timeout delay of 200 ms masks the propagation delay.
FUNCTIONAL TRUTH TABLE
Table 7.
MR
L
H
H
H
H
SENSE1 > V
IT1
X
1
0
0
1
1
SENSE2 > V
IT2
X
1
0
1
0
1
RESET
L
L
L
L
H
RESET
H
H
H
H
L
1
X = don’t care.
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