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參數資料
| 型號： | ADM238LJR |
| 廠商： | ANALOG DEVICES INC |
| 元件分類： | 通用總線功能 |
| 英文描述： | 5V High-Speed RS-232 Transceivers with 0.1uF Capacitors |
| 中文描述： | QUAD LINE TRANSCEIVER, PDSO24 |
| 封裝： | MS-013AD, SOIC-24 |
| 文件頁數： | 13/16頁 |
| 文件大小： | 364K |
| 代理商： | ADM238LJR |
ADM223/ADM230L–ADM241L
–13–
REV. 0
E nable Input
T he ADM235, ADM239, ADM241L and ADM223 feature an
enable input used to enable or disable the receiver outputs. T he
enable input is active low on the ADM235L, ADM239L,
ADM241L and active high on the ADM223. Refer to T ables I
and II. When disabled, all receiver outputs are placed in a high
impedance state. T his function allows the outputs to be con-
nected directly to a microprocessor data bus. It can also be used
to allow receivers from different devices to share a common data
line. T he timing diagram for the enable function is shown in
Figure 35.
T
EN
T
DIS
3V
0V
R
OUT
3.5V
0.8V
V
OH
– 0.1V
V
VOL
+ 0.1V
EN*
*POLARITY OF EN IS REVERSED FOR ADM223.
Figure 35. Enable Timing
APPLICAT ION HINT S
Driving Long Cables
In accordance with the EIA-232-E standard, long cables are per-
missible provided that the total load capacitance does not exceed
2500 pF. For longer cables which do exceed this, then it is pos-
sible to trade off baud rate vs. cable length. Large load capaci-
tances cause a reduction in slew rate, and hence the maximum
transmission baud rate is decreased. T he ADM230L-ADM241L
are designed so that the slew rate reduction with increasing load
capacitance is minimized.
For the receivers, it is important that a high level of noise immu-
nity be inbuilt so that slow rise and fall times do not cause mul-
tiple output transitions as the signal passes slowly through the
transition region. T he ADM230L-ADM241L have 0.5 V of hys-
teresis to guard against this. T his ensures that, even in noisy en-
vironments, error-free reception can be achieved.
High Baud Rate Operation
T he ADM230L-ADM241L feature high slew rates permitting
data transmission at rates well in excess of the EIA-232-E speci-
fication. T he drivers maintain
±
5 V signal levels at data rates up
to 100-kB/s under worst-case loading conditions.
S1
S3
S2
S4
INTERNAL
OSCILLATOR
C2
C4
V– = – (V+)
GND
V+
GND
FROM
VOLTAGE
DOUBLER
Figure 34. Charge-Pump Voltage Inverter
Capacitors C3 and C4 are used to reduce the output ripple.
T heir values are not critical and can be reduced if higher levels
of ripple are acceptable. T he charge pump capacitors C1 and
C2 may also be reduced at the expense of higher output imped-
ance on the V+ and V– supplies.
T he V+ and V– supplies may also be used to power external cir-
cuitry if the current requirements are small.
T ransmitter (Driver) Section
T he drivers convert T T L/CMOS input levels into EIA-232-E
output levels. With V
CC
= +5 V and driving a typical EIA-232-E
load, the output voltage swing is
±
9 V. Even under worst case
conditions the drivers are guaranteed to meet the
±
5 V
EIA-232-E minimum requirement.
T he input threshold levels are both T T L and CMOS compat-
ible with the switching threshold set at V
CC
/4. With a nominal
V
CC
= 5 V the switching threshold is 1.25 V typical. Unused in-
puts may be left unconnected, as an internal 400 k
pull-up re-
sistor pulls them high forcing the outputs into a low state.
As required by the EIA-232-E standard, the slew rate is limited
to less than 30 V/
μ
s without the need for an external slew limit-
ing capacitor and the output impedance in the power-off state is
greater than 300
.
Receiver Section
T he receivers are inverting level shifters which accept EIA-
232-E input levels (
±
5 V to
±
15 V) and translate them into 5 V
T T L/CMOS levels. T he inputs have internal 5 k
pull-down
resistors to ground and are also protected against overvoltages of
up to
±
30 V. T he guaranteed switching thresholds are 0.8 V
minimum and 2.4 V maximum which are well within the
±
3 V
EIA-232-E requirement. T he low level threshold is deliberately
positive as it ensures that an unconnected input will be inter-
preted as a low level.
T he receivers have Schmitt trigger inputs with a hysteresis level
of 0.5 V. T his ensures error-free reception for both noisy inputs
and for inputs with slow transition times.
Shutdown (SD)
T he ADM223, ADM230L, ADM235L, ADM236L and
ADM241L feature a control input that may be used to disable
the part and reduce the power consumption to less than 5
μ
W.
T his is very useful in battery operated systems. During shut-
down the charge pump is turned off, the transmitters are dis-
abled and all receivers except R4 and R5 on the ADM223 are
put into a high-impedance disabled state. Receivers R4 and R5
on the ADM223 remain enabled during shutdown. T his feature
allows monitoring external activity such as ring indicator moni-
toring while the device is in a low power shutdown mode.
T he shutdown control input is active high on all parts except the
ADM223 where it is active low. Refer to T ables I and II.
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相關代理商/技術參數 |
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| ADM238LJRZ | 功能描述:IC TX/RX QUAD RS-232 5VLP 24SOIC RoHS:是 類別:集成電路 (IC) >> 接口 - 驅動器，接收器，收發器 系列:- 產品培訓模塊:RS-232 & USB Transceiver 標準包裝:2,000 系列:- 類型:收發器 驅動器/接收器數:1/1 規程:RS232 電源電壓:3 V ~ 5.5 V 安裝類型:表面貼裝 封裝/外殼:16-SSOP（0.209"，5.30mm 寬） 供應商設備封裝:16-SSOP 包裝:帶卷 (TR) 其它名稱:296-19849-2 |
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