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參數(shù)資料
| 型號： | ADM3088AN |
| 廠商： | ANALOG DEVICES INC |
| 元件分類： | 通用總線功能 |
| 英文描述： | High-Speed (10Mbps), Fail-Safe, RS-485/RS-422 Transceivers with Slew-Rate-Limiting and 5kV ESD Protection |
| 中文描述： | LINE TRANSCEIVER, PDIP8 |
| 封裝： | PLASTIC, DIP-8 |
| 文件頁數(shù)： | 7/14頁 |
| 文件大小： | 316K |
| 代理商： | ADM3088AN |
ADM3082/ADM3085/ADM3088
–7–
PRELIMINARY TECHNICAL DATA
ADM3082/ADM3085/ADM3088 TEST CIRCUITS AND TIMING
R
R
V
OD
V
OC
Y
Z
Figure 1. Driver DC Load Test Circuit
R
DIFF
V
OD2
C
L1
C
L2
3V
DE
DI
Figure 2. Test Load for Driver Timing Tests
DI
Z
Y
V
0
/2
V
0
t
DF
V
DIFF
V
0
0
-V
0
90%
10%
t
DR
90%
10%
t
SKEW
= |t
DPLH
-t
DPHL
|
5V
0V
1.5V
t
DPLH
t
DPHL
V
DIFF
= V
Y
- V
Z
Figure 3. Driver Propagation Delays
RO
A
B
1V
-1V
V
OH
V
OL
1.5V
t
RPLH
t
RPHL
Figure 4. Receiver Propagation Delays
V
CC
S1
S2
TEST
POINT
C
RL
15pF
500
V
OUTPUT
UNDER
TEST
Figure 5. Test Load for Driver Enable/Disable Time Test
5V
0V
DE
Y, Z
V
OL
Y, Z
t
DZL(SHDN)
, t
DZL
t
DLZ
OUTPUT NORMALLY LOW
OUTPUT NORMALLY HIGH
1.5V
2.3V
V
OL
+0.5V
V
OH
-0.5V
V
OL
t
DZH(SHDN)
t
DZH
t
DHZ
2.3V
Figure 6. Driver Enable and Disable Times
RO
TEST
POINT
V
CC
1k
V
1k
V
S1
S2
C
RL
15pF
Figure 7. Test Load for Receiver Enable/Disable Time Test
OUTPUT NORMALLY LOW
OUTPUT NORMALLY HIGH
5V
0V
RE
RO
RO
t
RZL(SHDN)
, t
RZL
t
RLZ
1.5V
V
OL
+0.5V
V
OH
-0.5V
0V
t
RZH(SHDN)
, t
RZH
t
RHZ
1.5V
V
CC
1.5V
Figure 8. Receiver Enable and Disable Delay Times
REV. PrA 02/02
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