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參數(shù)資料
型號(hào): ADM5180JP
廠商: ANALOG DEVICES INC
元件分類: 通用總線功能
英文描述: Octal, RS-232/RS-423 Line Receiver
中文描述: LINE RECEIVER, PQCC28
封裝: PLASTIC, LCC-28
文件頁(yè)數(shù): 1/6頁(yè)
文件大小: 101K
代理商: ADM5180JP
ADM5180
FUNCT IONAL BLOCK DIAGRAM
REV. 0
Information furnished by Analog Devices is believed to be accurate and
reliable. However, no responsibility is assumed by Analog Devices for its
use, nor for any infringements of patents or other rights of third parties
which may result from its use. No license is granted by implication or
otherwise under any patent or patent rights of Analog Devices.
FEATURES
Eight Differential Line Receivers in One Package
Meets EIA Standard EIA-232E, 423A, 422A and
CCITT V.10, V.11, V.28
Single +5 V Supply
Differential Inputs Withstand
±
25 V
Internal Hysteresis
Low Power CMOS –3.5 mA Supply Current
TTL/CMOS Compatible Outputs
Available in 28-Pin DIP and PLCC Packages
Low Power Replacement for UC5180C/NE5180
APPLICATIONS
High Speed Communication
Computer I-O Ports
Peripherals
High Speed Modems
Printers
Logic Level Translation
One Technology Way, P.O. Box 9106, Norwood. MA 02062-9106, U.S.A.
Tel: 617/329-4700
Fax: 617/326-8703
a
Octal, RS-232/RS-423 Line Receiver
GE NE RAL DE SCRIPT ION
T he ADM5180 is an octal differential line receiver suitable for a
wide range of digital communication systems with data rates up to
200 kB/s. Input signals conforming to EIA Standards 232-E, 422A
and CCIT T V.10, V.11, V.28, X .26, and X .27 are accepted and
translated into T T L /CMOS output signal levels.
T he ADM5180 is a superior upgrade for the UC5180C and the
NE5180. It is fabricated on an advanced BiCMOS process,
allowing high speed bipolar circuitry to be combined with low
power CMOS. T his minimizes the power consumption to less than
25 mW.
A failsafe function ensures a known output state under a variety of
input fault conditions as defined in RS-422A and RS-423A. T he
failsafe function is controlled by FS1 and FS2. Each controls four
receivers. With FS = Low and a fault condition the output is forced
low while if FS = High, the output is forced high.
T he device is available in both 28-pin DIP and 28-lead PLCC
packages.
T ruth T able
Differential Input
(+) - (–)
Failsafe Input
FS1, FS2
Receiver
Logic Output
>200 mV
<–200 mV
O/C
S/C
O/C
S/C
X
X
L
L
H
H
H
L
L
L
H
H
A
B
C
D
E
F
G
H
A–
A+
B–
B+
C–
C+
D–
D+
E–
E+
F–
F+
G–
G+
H–
H+
A
O
B
O
C
O
D
O
E
O
F
O
G
O
H
O
FS1
FS2
ADM5180
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